[llvm] r295783 - AMDGPU: Formatting fixes
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 21 14:50:41 PST 2017
Author: arsenm
Date: Tue Feb 21 16:50:41 2017
New Revision: 295783
URL: http://llvm.org/viewvc/llvm-project?rev=295783&view=rev
Log:
AMDGPU: Formatting fixes
Modified:
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=295783&r1=295782&r2=295783&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Tue Feb 21 16:50:41 2017
@@ -1533,11 +1533,12 @@ static bool setM0ToIndexFromSGPR(const S
}
if (Offset == 0) {
- BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0).add(*Idx);
+ BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
+ .add(*Idx);
} else {
BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
- .add(*Idx)
- .addImm(Offset);
+ .add(*Idx)
+ .addImm(Offset);
}
return true;
@@ -2872,7 +2873,7 @@ SDValue SITargetLowering::LowerINTRINSIC
unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
switch (IntrinsicID) {
- case Intrinsic::amdgcn_exp: {
+ case Intrinsic::amdgcn_exp: {
const ConstantSDNode *Tgt = cast<ConstantSDNode>(Op.getOperand(2));
const ConstantSDNode *En = cast<ConstantSDNode>(Op.getOperand(3));
const ConstantSDNode *Done = cast<ConstantSDNode>(Op.getOperand(8));
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