[llvm] r295773 - [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
Eugene Zelenko via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 21 14:07:52 PST 2017
Author: eugenezelenko
Date: Tue Feb 21 16:07:52 2017
New Revision: 295773
URL: http://llvm.org/viewvc/llvm-project?rev=295773&view=rev
Log:
[CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
Modified:
llvm/trunk/include/llvm/CodeGen/MachineTraceMetrics.h
llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h
llvm/trunk/include/llvm/CodeGen/RegisterClassInfo.h
llvm/trunk/include/llvm/CodeGen/RegisterPressure.h
llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h
llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp
llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp
llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp
llvm/trunk/lib/CodeGen/RegisterPressure.cpp
llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MachineTraceMetrics.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineTraceMetrics.h?rev=295773&r1=295772&r2=295773&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineTraceMetrics.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineTraceMetrics.h Tue Feb 21 16:07:52 2017
@@ -49,54 +49,59 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/None.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/TargetSchedule.h"
namespace llvm {
-class InstrItineraryData;
+class AnalysisUsage;
class MachineBasicBlock;
+class MachineFunction;
class MachineInstr;
class MachineLoop;
class MachineLoopInfo;
class MachineRegisterInfo;
+struct MCSchedClassDesc;
+class raw_ostream;
class TargetInstrInfo;
class TargetRegisterInfo;
-class raw_ostream;
class MachineTraceMetrics : public MachineFunctionPass {
- const MachineFunction *MF;
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
- const MachineRegisterInfo *MRI;
- const MachineLoopInfo *Loops;
+ const MachineFunction *MF = nullptr;
+ const TargetInstrInfo *TII = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ const MachineRegisterInfo *MRI = nullptr;
+ const MachineLoopInfo *Loops = nullptr;
TargetSchedModel SchedModel;
public:
+ friend class Ensemble;
+ friend class Trace;
+
class Ensemble;
- class Trace;
+
static char ID;
+
MachineTraceMetrics();
+
void getAnalysisUsage(AnalysisUsage&) const override;
bool runOnMachineFunction(MachineFunction&) override;
void releaseMemory() override;
void verifyAnalysis() const override;
- friend class Ensemble;
- friend class Trace;
-
/// Per-basic block information that doesn't depend on the trace through the
/// block.
struct FixedBlockInfo {
/// The number of non-trivial instructions in the block.
/// Doesn't count PHI and COPY instructions that are likely to be removed.
- unsigned InstrCount;
+ unsigned InstrCount = ~0u;
/// True when the block contains calls.
- bool HasCalls;
+ bool HasCalls = false;
- FixedBlockInfo() : InstrCount(~0u), HasCalls(false) {}
+ FixedBlockInfo() = default;
/// Returns true when resource information for this block has been computed.
bool hasResources() const { return InstrCount != ~0u; }
@@ -134,11 +139,11 @@ public:
struct TraceBlockInfo {
/// Trace predecessor, or NULL for the first block in the trace.
/// Valid when hasValidDepth().
- const MachineBasicBlock *Pred;
+ const MachineBasicBlock *Pred = nullptr;
/// Trace successor, or NULL for the last block in the trace.
/// Valid when hasValidHeight().
- const MachineBasicBlock *Succ;
+ const MachineBasicBlock *Succ = nullptr;
/// The block number of the head of the trace. (When hasValidDepth()).
unsigned Head;
@@ -148,16 +153,13 @@ public:
/// Accumulated number of instructions in the trace above this block.
/// Does not include instructions in this block.
- unsigned InstrDepth;
+ unsigned InstrDepth = ~0u;
/// Accumulated number of instructions in the trace below this block.
/// Includes instructions in this block.
- unsigned InstrHeight;
+ unsigned InstrHeight = ~0u;
- TraceBlockInfo() :
- Pred(nullptr), Succ(nullptr),
- InstrDepth(~0u), InstrHeight(~0u),
- HasValidInstrDepths(false), HasValidInstrHeights(false) {}
+ TraceBlockInfo() = default;
/// Returns true if the depth resources have been computed from the trace
/// above this block.
@@ -199,10 +201,10 @@ public:
// itinerary data.
/// Instruction depths have been computed. This implies hasValidDepth().
- bool HasValidInstrDepths;
+ bool HasValidInstrDepths = false;
/// Instruction heights have been computed. This implies hasValidHeight().
- bool HasValidInstrHeights;
+ bool HasValidInstrHeights = false;
/// Critical path length. This is the number of cycles in the longest data
/// dependency chain through the trace. This is only valid when both
@@ -242,6 +244,7 @@ public:
public:
explicit Trace(Ensemble &te, TraceBlockInfo &tbi) : TE(te), TBI(tbi) {}
+
void print(raw_ostream&) const;
/// Compute the total number of instructions in the trace.
@@ -300,11 +303,12 @@ public:
/// strategy, for example 'minimum resource height'. There is one trace for
/// every block in the function.
class Ensemble {
+ friend class Trace;
+
SmallVector<TraceBlockInfo, 4> BlockInfo;
DenseMap<const MachineInstr*, InstrCycles> Cycles;
SmallVector<unsigned, 0> ProcResourceDepths;
SmallVector<unsigned, 0> ProcResourceHeights;
- friend class Trace;
void computeTrace(const MachineBasicBlock*);
void computeDepthResources(const MachineBasicBlock*);
@@ -317,9 +321,11 @@ public:
protected:
MachineTraceMetrics &MTM;
+
+ explicit Ensemble(MachineTraceMetrics*);
+
virtual const MachineBasicBlock *pickTracePred(const MachineBasicBlock*) =0;
virtual const MachineBasicBlock *pickTraceSucc(const MachineBasicBlock*) =0;
- explicit Ensemble(MachineTraceMetrics*);
const MachineLoop *getLoopFor(const MachineBasicBlock*) const;
const TraceBlockInfo *getDepthResources(const MachineBasicBlock*) const;
const TraceBlockInfo *getHeightResources(const MachineBasicBlock*) const;
@@ -328,7 +334,8 @@ public:
public:
virtual ~Ensemble();
- virtual const char *getName() const =0;
+
+ virtual const char *getName() const = 0;
void print(raw_ostream&) const;
void invalidate(const MachineBasicBlock *MBB);
void verify() const;
@@ -394,6 +401,7 @@ inline raw_ostream &operator<<(raw_ostre
En.print(OS);
return OS;
}
+
} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_MACHINETRACEMETRICS_H
Modified: llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h?rev=295773&r1=295772&r2=295773&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h (original)
+++ llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h Tue Feb 21 16:07:52 2017
@@ -1,4 +1,4 @@
-//===-- RegAllocPBQP.h ------------------------------------------*- C++ -*-===//
+//===- RegAllocPBQP.h -------------------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -16,15 +16,28 @@
#ifndef LLVM_CODEGEN_REGALLOCPBQP_H
#define LLVM_CODEGEN_REGALLOCPBQP_H
-#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/Hashing.h"
#include "llvm/CodeGen/PBQP/CostAllocator.h"
+#include "llvm/CodeGen/PBQP/Graph.h"
+#include "llvm/CodeGen/PBQP/Math.h"
#include "llvm/CodeGen/PBQP/ReductionRules.h"
-#include "llvm/CodeGen/PBQPRAConstraint.h"
+#include "llvm/CodeGen/PBQP/Solution.h"
#include "llvm/Support/ErrorHandling.h"
+#include <algorithm>
+#include <cassert>
+#include <cstddef>
+#include <limits>
+#include <memory>
#include <set>
+#include <vector>
namespace llvm {
+class FunctionPass;
+class LiveIntervals;
+class MachineBlockFrequencyInfo;
+class MachineFunction;
class raw_ostream;
namespace PBQP {
@@ -37,15 +50,10 @@ inline unsigned getSpillOptionIdx() { re
///
/// Keeps track of the number of infinities in each row and column.
class MatrixMetadata {
-private:
- MatrixMetadata(const MatrixMetadata&);
- void operator=(const MatrixMetadata&);
public:
MatrixMetadata(const Matrix& M)
- : WorstRow(0), WorstCol(0),
- UnsafeRows(new bool[M.getRows() - 1]()),
+ : UnsafeRows(new bool[M.getRows() - 1]()),
UnsafeCols(new bool[M.getCols() - 1]()) {
-
unsigned* ColCounts = new unsigned[M.getCols() - 1]();
for (unsigned i = 1; i < M.getRows(); ++i) {
@@ -66,13 +74,17 @@ public:
delete[] ColCounts;
}
+ MatrixMetadata(const MatrixMetadata &) = delete;
+ MatrixMetadata &operator=(const MatrixMetadata &) = delete;
+
unsigned getWorstRow() const { return WorstRow; }
unsigned getWorstCol() const { return WorstCol; }
const bool* getUnsafeRows() const { return UnsafeRows.get(); }
const bool* getUnsafeCols() const { return UnsafeCols.get(); }
private:
- unsigned WorstRow, WorstCol;
+ unsigned WorstRow = 0;
+ unsigned WorstCol = 0;
std::unique_ptr<bool[]> UnsafeRows;
std::unique_ptr<bool[]> UnsafeCols;
};
@@ -80,17 +92,16 @@ private:
/// \brief Holds a vector of the allowed physical regs for a vreg.
class AllowedRegVector {
friend hash_code hash_value(const AllowedRegVector &);
-public:
- AllowedRegVector() : NumOpts(0), Opts(nullptr) {}
+public:
+ AllowedRegVector() = default;
+ AllowedRegVector(AllowedRegVector &&) = default;
AllowedRegVector(const std::vector<unsigned> &OptVec)
: NumOpts(OptVec.size()), Opts(new unsigned[NumOpts]) {
std::copy(OptVec.begin(), OptVec.end(), Opts.get());
}
- AllowedRegVector(AllowedRegVector &&) = default;
-
unsigned size() const { return NumOpts; }
unsigned operator[](size_t I) const { return Opts[I]; }
@@ -105,7 +116,7 @@ public:
}
private:
- unsigned NumOpts;
+ unsigned NumOpts = 0;
std::unique_ptr<unsigned[]> Opts;
};
@@ -120,8 +131,8 @@ inline hash_code hash_value(const Allowe
class GraphMetadata {
private:
typedef ValuePool<AllowedRegVector> AllowedRegVecPool;
-public:
+public:
typedef AllowedRegVecPool::PoolRef AllowedRegVecRef;
GraphMetadata(MachineFunction &MF,
@@ -168,13 +179,7 @@ public:
OptimallyReducible
} ReductionState;
- NodeMetadata()
- : RS(Unprocessed), NumOpts(0), DeniedOpts(0), OptUnsafeEdges(nullptr),
- VReg(0)
-#ifndef NDEBUG
- , everConservativelyAllocatable(false)
-#endif
- {}
+ NodeMetadata() = default;
NodeMetadata(const NodeMetadata &Other)
: RS(Other.RS), NumOpts(Other.NumOpts), DeniedOpts(Other.DeniedOpts),
@@ -190,9 +195,8 @@ public:
}
}
- NodeMetadata(NodeMetadata &&Other) = default;
-
- NodeMetadata& operator=(NodeMetadata &&Other) = default;
+ NodeMetadata(NodeMetadata &&) = default;
+ NodeMetadata& operator=(NodeMetadata &&) = default;
void setVReg(unsigned VReg) { this->VReg = VReg; }
unsigned getVReg() const { return VReg; }
@@ -249,21 +253,22 @@ public:
#endif
private:
- ReductionState RS;
- unsigned NumOpts;
- unsigned DeniedOpts;
+ ReductionState RS = Unprocessed;
+ unsigned NumOpts = 0;
+ unsigned DeniedOpts = 0;
std::unique_ptr<unsigned[]> OptUnsafeEdges;
- unsigned VReg;
+ unsigned VReg = 0;
GraphMetadata::AllowedRegVecRef AllowedRegs;
#ifndef NDEBUG
- bool everConservativelyAllocatable;
+ bool everConservativelyAllocatable = false;
#endif
};
class RegAllocSolverImpl {
private:
typedef MDMatrix<MatrixMetadata> RAMatrix;
+
public:
typedef PBQP::Vector RawVector;
typedef PBQP::Matrix RawMatrix;
@@ -296,6 +301,7 @@ public:
"PBQP Graph should not contain single or zero-option nodes");
G.getNodeMetadata(NId).setup(G.getNodeCosts(NId));
}
+
void handleRemoveNode(NodeId NId) {}
void handleSetNodeCosts(NodeId NId, const Vector& newCosts) {}
@@ -342,7 +348,6 @@ public:
}
private:
-
void promote(NodeId NId, NodeMetadata& NMd) {
if (G.getNodeDegree(NId) == 3) {
// This node is becoming optimally reducible.
@@ -474,6 +479,7 @@ private:
class SpillCostComparator {
public:
SpillCostComparator(const Graph& G) : G(G) {}
+
bool operator()(NodeId N1Id, NodeId N2Id) {
PBQPNum N1SC = G.getNodeCosts(N1Id)[0];
PBQPNum N2SC = G.getNodeCosts(N2Id)[0];
@@ -481,6 +487,7 @@ private:
return G.getNodeDegree(N1Id) < G.getNodeDegree(N2Id);
return N1SC < N2SC;
}
+
private:
const Graph& G;
};
@@ -495,6 +502,7 @@ private:
class PBQPRAGraph : public PBQP::Graph<RegAllocSolverImpl> {
private:
typedef PBQP::Graph<RegAllocSolverImpl> BaseT;
+
public:
PBQPRAGraph(GraphMetadata Metadata) : BaseT(std::move(Metadata)) {}
@@ -517,13 +525,13 @@ inline Solution solve(PBQPRAGraph& G) {
return RegAllocSolver.solve();
}
-} // namespace RegAlloc
-} // namespace PBQP
+} // end namespace RegAlloc
+} // end namespace PBQP
/// @brief Create a PBQP register allocator instance.
FunctionPass *
createPBQPRegisterAllocator(char *customPassID = nullptr);
-} // namespace llvm
+} // end namespace llvm
-#endif /* LLVM_CODEGEN_REGALLOCPBQP_H */
+#endif // LLVM_CODEGEN_REGALLOCPBQP_H
Modified: llvm/trunk/include/llvm/CodeGen/RegisterClassInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterClassInfo.h?rev=295773&r1=295772&r2=295773&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/RegisterClassInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/RegisterClassInfo.h Tue Feb 21 16:07:52 2017
@@ -1,4 +1,4 @@
-//===-- RegisterClassInfo.h - Dynamic Register Class Info -*- C++ -*-------===//
+//===- RegisterClassInfo.h - Dynamic Register Class Info --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -19,22 +19,25 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
+#include <cassert>
+#include <cstdint>
+#include <memory>
namespace llvm {
class RegisterClassInfo {
struct RCInfo {
- unsigned Tag;
- unsigned NumRegs;
- bool ProperSubClass;
- uint8_t MinCost;
- uint16_t LastCostChange;
+ unsigned Tag = 0;
+ unsigned NumRegs = 0;
+ bool ProperSubClass = false;
+ uint8_t MinCost = 0;
+ uint16_t LastCostChange = 0;
std::unique_ptr<MCPhysReg[]> Order;
- RCInfo()
- : Tag(0), NumRegs(0), ProperSubClass(false), MinCost(0),
- LastCostChange(0) {}
+ RCInfo() = default;
operator ArrayRef<MCPhysReg>() const {
return makeArrayRef(Order.get(), NumRegs);
@@ -46,14 +49,14 @@ class RegisterClassInfo {
// Tag changes whenever cached information needs to be recomputed. An RCInfo
// entry is valid when its tag matches.
- unsigned Tag;
+ unsigned Tag = 0;
- const MachineFunction *MF;
- const TargetRegisterInfo *TRI;
+ const MachineFunction *MF = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
// Callee saved registers of last MF. Assumed to be valid until the next
// runOnFunction() call.
- const MCPhysReg *CalleeSaved;
+ const MCPhysReg *CalleeSaved = nullptr;
// Map register number to CalleeSaved index + 1;
SmallVector<uint8_t, 4> CSRNum;
@@ -140,6 +143,7 @@ public:
protected:
unsigned computePSetLimit(unsigned Idx) const;
};
+
} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_REGISTERCLASSINFO_H
Modified: llvm/trunk/include/llvm/CodeGen/RegisterPressure.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterPressure.h?rev=295773&r1=295772&r2=295773&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/RegisterPressure.h (original)
+++ llvm/trunk/include/llvm/CodeGen/RegisterPressure.h Tue Feb 21 16:07:52 2017
@@ -1,4 +1,4 @@
-//===-- RegisterPressure.h - Dynamic Register Pressure -*- C++ -*-------===//
+//===- RegisterPressure.h - Dynamic Register Pressure -----------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -15,16 +15,25 @@
#ifndef LLVM_CODEGEN_REGISTERPRESSURE_H
#define LLVM_CODEGEN_REGISTERPRESSURE_H
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SparseSet.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/MC/LaneBitmask.h"
#include "llvm/Target/TargetRegisterInfo.h"
+#include <cassert>
+#include <cstddef>
+#include <cstdint>
+#include <cstdlib>
+#include <limits>
+#include <vector>
namespace llvm {
class LiveIntervals;
-class LiveRange;
-class RegisterClassInfo;
class MachineInstr;
+class RegisterClassInfo;
struct RegisterMaskPair {
unsigned RegUnit; ///< Virtual register or register unit.
@@ -91,12 +100,13 @@ struct RegionPressure : RegisterPressure
/// higher level assert that pressure is consistent within a region. We also
/// effectively ignore dead defs which don't affect heuristics much.
class PressureChange {
- uint16_t PSetID; // ID+1. 0=Invalid.
- int16_t UnitInc;
+ uint16_t PSetID = 0; // ID+1. 0=Invalid.
+ int16_t UnitInc = 0;
+
public:
- PressureChange(): PSetID(0), UnitInc(0) {}
- PressureChange(unsigned id): PSetID(id+1), UnitInc(0) {
- assert(id < UINT16_MAX && "PSetID overflow.");
+ PressureChange() = default;
+ PressureChange(unsigned id): PSetID(id + 1) {
+ assert(id < std::numeric_limits<uint16_t>::max() && "PSetID overflow.");
}
bool isValid() const { return PSetID > 0; }
@@ -105,8 +115,11 @@ public:
assert(isValid() && "invalid PressureChange");
return PSetID - 1;
}
+
// If PSetID is invalid, return UINT16_MAX to give it lowest priority.
- unsigned getPSetOrMax() const { return (PSetID - 1) & UINT16_MAX; }
+ unsigned getPSetOrMax() const {
+ return (PSetID - 1) & std::numeric_limits<uint16_t>::max();
+ }
int getUnitInc() const { return UnitInc; }
@@ -182,11 +195,12 @@ public:
/// Array of PressureDiffs.
class PressureDiffs {
- PressureDiff *PDiffArray;
- unsigned Size;
- unsigned Max;
+ PressureDiff *PDiffArray = nullptr;
+ unsigned Size = 0;
+ unsigned Max = 0;
+
public:
- PressureDiffs(): PDiffArray(nullptr), Size(0), Max(0) {}
+ PressureDiffs() = default;
~PressureDiffs() { free(PDiffArray); }
void clear() { Size = 0; }
@@ -200,6 +214,7 @@ public:
const PressureDiff &operator[](unsigned Idx) const {
return const_cast<PressureDiffs*>(this)->operator[](Idx);
}
+
/// \brief Record pressure difference induced by the given operand list to
/// node with index \p Idx.
void addInstruction(unsigned Idx, const RegisterOperands &RegOpers,
@@ -225,7 +240,7 @@ struct RegPressureDelta {
PressureChange CriticalMax;
PressureChange CurrentMax;
- RegPressureDelta() {}
+ RegPressureDelta() = default;
bool operator==(const RegPressureDelta &RHS) const {
return Excess == RHS.Excess && CriticalMax == RHS.CriticalMax
@@ -264,6 +279,7 @@ private:
assert(Reg < NumRegUnits);
return Reg;
}
+
unsigned getRegFromSparseIndex(unsigned SparseIndex) const {
if (SparseIndex >= NumRegUnits)
return TargetRegisterInfo::index2VirtReg(SparseIndex-NumRegUnits);
@@ -338,14 +354,14 @@ public:
/// tracking. Changing direction has the side effect of closing region, and
/// traversing past TopIdx or BottomIdx reopens it.
class RegPressureTracker {
- const MachineFunction *MF;
- const TargetRegisterInfo *TRI;
- const RegisterClassInfo *RCI;
+ const MachineFunction *MF = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ const RegisterClassInfo *RCI = nullptr;
const MachineRegisterInfo *MRI;
- const LiveIntervals *LIS;
+ const LiveIntervals *LIS = nullptr;
/// We currently only allow pressure tracking within a block.
- const MachineBasicBlock *MBB;
+ const MachineBasicBlock *MBB = nullptr;
/// Track the max pressure within the region traversed so far.
RegisterPressure &P;
@@ -355,10 +371,10 @@ class RegPressureTracker {
bool RequireIntervals;
/// True if UntiedDefs will be populated.
- bool TrackUntiedDefs;
+ bool TrackUntiedDefs = false;
/// True if lanemasks should be tracked.
- bool TrackLaneMasks;
+ bool TrackLaneMasks = false;
/// Register pressure corresponds to liveness before this instruction
/// iterator. It may point to the end of the block or a DebugValue rather than
@@ -377,13 +393,8 @@ class RegPressureTracker {
std::vector<unsigned> LiveThruPressure;
public:
- RegPressureTracker(IntervalPressure &rp) :
- MF(nullptr), TRI(nullptr), RCI(nullptr), LIS(nullptr), MBB(nullptr), P(rp),
- RequireIntervals(true), TrackUntiedDefs(false), TrackLaneMasks(false) {}
-
- RegPressureTracker(RegionPressure &rp) :
- MF(nullptr), TRI(nullptr), RCI(nullptr), LIS(nullptr), MBB(nullptr), P(rp),
- RequireIntervals(false), TrackUntiedDefs(false), TrackLaneMasks(false) {}
+ RegPressureTracker(IntervalPressure &rp) : P(rp), RequireIntervals(true) {}
+ RegPressureTracker(RegionPressure &rp) : P(rp), RequireIntervals(false) {}
void reset();
@@ -555,6 +566,7 @@ protected:
void dumpRegSetPressure(ArrayRef<unsigned> SetPressure,
const TargetRegisterInfo *TRI);
+
} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_REGISTERPRESSURE_H
Modified: llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h?rev=295773&r1=295772&r2=295773&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h (original)
+++ llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h Tue Feb 21 16:07:52 2017
@@ -1,4 +1,4 @@
-//===-- RegisterScavenging.h - Machine register scavenging ------*- C++ -*-===//
+//===- RegisterScavenging.h - Machine register scavenging -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -19,41 +19,43 @@
#define LLVM_CODEGEN_REGISTERSCAVENGING_H
#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/LiveRegUnits.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/MC/LaneBitmask.h"
namespace llvm {
-class MachineRegisterInfo;
-class TargetRegisterInfo;
+class MachineInstr;
class TargetInstrInfo;
class TargetRegisterClass;
+class TargetRegisterInfo;
class RegScavenger {
const TargetRegisterInfo *TRI;
const TargetInstrInfo *TII;
MachineRegisterInfo* MRI;
- MachineBasicBlock *MBB;
+ MachineBasicBlock *MBB = nullptr;
MachineBasicBlock::iterator MBBI;
- unsigned NumRegUnits;
+ unsigned NumRegUnits = 0;
/// True if RegScavenger is currently tracking the liveness of registers.
- bool Tracking;
+ bool Tracking = false;
/// Information on scavenged registers (held in a spill slot).
struct ScavengedInfo {
- ScavengedInfo(int FI = -1) : FrameIndex(FI), Reg(0), Restore(nullptr) {}
+ ScavengedInfo(int FI = -1) : FrameIndex(FI) {}
/// A spill slot used for scavenging a register post register allocation.
int FrameIndex;
/// If non-zero, the specific register is currently being
/// scavenged. That is, it is spilled to this scavenging stack slot.
- unsigned Reg;
+ unsigned Reg = 0;
/// The instruction that restores the scavenged register from stack.
- const MachineInstr *Restore;
+ const MachineInstr *Restore = nullptr;
};
/// A vector of information on scavenged registers.
@@ -67,8 +69,7 @@ class RegScavenger {
BitVector TmpRegUnits;
public:
- RegScavenger()
- : MBB(nullptr), NumRegUnits(0), Tracking(false) {}
+ RegScavenger() = default;
/// Start tracking liveness from the begin of basic block \p MBB.
void enterBasicBlock(MachineBasicBlock &MBB);
@@ -163,6 +164,7 @@ public:
/// Tell the scavenger a register is used.
void setRegUsed(unsigned Reg, LaneBitmask LaneMask = LaneBitmask::getAll());
+
private:
/// Returns true if a register is reserved. It is never "unused".
bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
@@ -202,6 +204,6 @@ private:
void setLiveInsUsed(const MachineBasicBlock &MBB);
};
-} // End llvm namespace
+} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_REGISTERSCAVENGING_H
Modified: llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp?rev=295773&r1=295772&r2=295773&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp Tue Feb 21 16:07:52 2017
@@ -1,4 +1,4 @@
-//===- lib/CodeGen/MachineTraceMetrics.cpp ----------------------*- C++ -*-===//
+//===- lib/CodeGen/MachineTraceMetrics.cpp --------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,21 +7,35 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/CodeGen/MachineTraceMetrics.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/Optional.h"
#include "llvm/ADT/PostOrderIterator.h"
+#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SparseSet.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/CodeGen/MachineTraceMetrics.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
+#include <algorithm>
+#include <cassert>
+#include <iterator>
+#include <tuple>
+#include <utility>
using namespace llvm;
@@ -37,9 +51,7 @@ INITIALIZE_PASS_DEPENDENCY(MachineLoopIn
INITIALIZE_PASS_END(MachineTraceMetrics,
"machine-trace-metrics", "Machine Trace Metrics", false, true)
-MachineTraceMetrics::MachineTraceMetrics()
- : MachineFunctionPass(ID), MF(nullptr), TII(nullptr), TRI(nullptr),
- MRI(nullptr), Loops(nullptr) {
+MachineTraceMetrics::MachineTraceMetrics() : MachineFunctionPass(ID) {
std::fill(std::begin(Ensembles), std::end(Ensembles), nullptr);
}
@@ -137,7 +149,6 @@ MachineTraceMetrics::getProcResourceCycl
return makeArrayRef(ProcResourceCycles.data() + MBBNum * PRKinds, PRKinds);
}
-
//===----------------------------------------------------------------------===//
// Ensemble utility functions
//===----------------------------------------------------------------------===//
@@ -151,7 +162,7 @@ MachineTraceMetrics::Ensemble::Ensemble(
}
// Virtual destructor serves as an anchor.
-MachineTraceMetrics::Ensemble::~Ensemble() {}
+MachineTraceMetrics::Ensemble::~Ensemble() = default;
const MachineLoop*
MachineTraceMetrics::Ensemble::getLoopFor(const MachineBasicBlock *MBB) const {
@@ -297,6 +308,7 @@ static bool isExitingLoop(const MachineL
// MinInstrCountEnsemble - Pick the trace that executes the least number of
// instructions.
namespace {
+
class MinInstrCountEnsemble : public MachineTraceMetrics::Ensemble {
const char *getName() const override { return "MinInstr"; }
const MachineBasicBlock *pickTracePred(const MachineBasicBlock*) override;
@@ -306,7 +318,8 @@ public:
MinInstrCountEnsemble(MachineTraceMetrics *mtm)
: MachineTraceMetrics::Ensemble(mtm) {}
};
-}
+
+} // end anonymous namespace
// Select the preferred predecessor for MBB.
const MachineBasicBlock*
@@ -409,25 +422,30 @@ void MachineTraceMetrics::verifyAnalysis
// revisit blocks.
namespace {
+
struct LoopBounds {
MutableArrayRef<MachineTraceMetrics::TraceBlockInfo> Blocks;
SmallPtrSet<const MachineBasicBlock*, 8> Visited;
const MachineLoopInfo *Loops;
- bool Downward;
+ bool Downward = false;
+
LoopBounds(MutableArrayRef<MachineTraceMetrics::TraceBlockInfo> blocks,
- const MachineLoopInfo *loops)
- : Blocks(blocks), Loops(loops), Downward(false) {}
+ const MachineLoopInfo *loops) : Blocks(blocks), Loops(loops) {}
};
-}
+
+} // end anonymous namespace
// Specialize po_iterator_storage in order to prune the post-order traversal so
// it is limited to the current loop and doesn't traverse the loop back edges.
namespace llvm {
+
template<>
class po_iterator_storage<LoopBounds, true> {
LoopBounds &LB;
+
public:
po_iterator_storage(LoopBounds &lb) : LB(lb) {}
+
void finishPostorder(const MachineBasicBlock*) {}
bool insertEdge(Optional<const MachineBasicBlock *> From,
@@ -452,7 +470,8 @@ public:
return LB.Visited.insert(To).second;
}
};
-}
+
+} // end namespace llvm
/// Compute the trace through MBB.
void MachineTraceMetrics::Ensemble::computeTrace(const MachineBasicBlock *MBB) {
@@ -603,6 +622,7 @@ void MachineTraceMetrics::Ensemble::veri
// A data dependency is represented as a defining MI and operand numbers on the
// defining and using MI.
namespace {
+
struct DataDep {
const MachineInstr *DefMI;
unsigned DefOp;
@@ -622,7 +642,8 @@ struct DataDep {
assert((++DefI).atEnd() && "Register has multiple defs");
}
};
-}
+
+} // end anonymous namespace
// Get the input data dependencies that must be ready before UseMI can issue.
// Return true if UseMI has any physreg operands.
@@ -678,17 +699,19 @@ static void getPHIDeps(const MachineInst
// direction instructions are scanned, it could be the operand that defined the
// regunit, or the highest operand to read the regunit.
namespace {
+
struct LiveRegUnit {
unsigned RegUnit;
- unsigned Cycle;
- const MachineInstr *MI;
- unsigned Op;
+ unsigned Cycle = 0;
+ const MachineInstr *MI = nullptr;
+ unsigned Op = 0;
unsigned getSparseSetIndex() const { return RegUnit; }
- LiveRegUnit(unsigned RU) : RegUnit(RU), Cycle(0), MI(nullptr), Op(0) {}
+ LiveRegUnit(unsigned RU) : RegUnit(RU) {}
};
-}
+
+} // end anonymous namespace
// Identify physreg dependencies for UseMI, and update the live regunit
// tracking set when scanning instructions downwards.
@@ -922,7 +945,6 @@ static unsigned updatePhysDepsUpwards(co
return Height;
}
-
typedef DenseMap<const MachineInstr *, unsigned> MIHeightMap;
// Push the height of DefMI upwards if required to match UseMI.
Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=295773&r1=295772&r2=295773&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Tue Feb 21 16:07:52 2017
@@ -1,4 +1,4 @@
-//===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
+//===- RegAllocPBQP.cpp ---- PBQP Register Allocator ----------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -29,34 +29,61 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/CodeGen/RegAllocPBQP.h"
#include "RegisterCoalescer.h"
#include "Spiller.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/DenseSet.h"
+#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringRef.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/CalcSpillWeights.h"
+#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveRangeEdit.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/PBQP/Graph.h"
+#include "llvm/CodeGen/PBQP/Solution.h"
+#include "llvm/CodeGen/PBQPRAConstraint.h"
+#include "llvm/CodeGen/RegAllocPBQP.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/VirtRegMap.h"
+#include "llvm/IR/Function.h"
#include "llvm/IR/Module.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/FileSystem.h"
#include "llvm/Support/Printable.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
+#include <algorithm>
+#include <cassert>
+#include <cstddef>
#include <limits>
+#include <map>
#include <memory>
#include <queue>
#include <set>
#include <sstream>
+#include <string>
+#include <system_error>
+#include <tuple>
#include <vector>
+#include <utility>
using namespace llvm;
@@ -86,7 +113,6 @@ namespace {
/// Programming problems.
class RegAllocPBQP : public MachineFunctionPass {
public:
-
static char ID;
/// Construct a PBQP register allocator.
@@ -113,7 +139,6 @@ public:
}
private:
-
typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
typedef std::vector<const LiveInterval*> Node2LIMap;
typedef std::vector<unsigned> AllowedSet;
@@ -187,7 +212,6 @@ public:
/// @brief Add interference edges between overlapping vregs.
class Interference : public PBQPRAConstraint {
private:
-
typedef const PBQP::RegAlloc::AllowedRegVector* AllowedRegVecPtr;
typedef std::pair<AllowedRegVecPtr, AllowedRegVecPtr> IKey;
typedef DenseMap<IKey, PBQPRAGraph::MatrixPtr> IMatrixCache;
@@ -276,7 +300,6 @@ private:
}
public:
-
void apply(PBQPRAGraph &G) override {
// The following is loosely based on the linear scan algorithm introduced in
// "Linear Scan Register Allocation" by Poletto and Sarkar. This version
@@ -363,7 +386,6 @@ public:
}
private:
-
// Create an Interference edge and add it to the graph, unless it is
// a null matrix, meaning the nodes' allowed registers do not have any
// interference. This case occurs frequently between integer and floating
@@ -372,7 +394,6 @@ private:
bool createInterferenceEdge(PBQPRAGraph &G,
PBQPRAGraph::NodeId NId, PBQPRAGraph::NodeId MId,
IMatrixCache &C) {
-
const TargetRegisterInfo &TRI =
*G.getMetadata().MF.getSubtarget().getRegisterInfo();
const auto &NRegs = G.getNodeMetadata(NId).getAllowedRegs();
@@ -409,7 +430,6 @@ private:
}
};
-
class Coalescing : public PBQPRAConstraint {
public:
void apply(PBQPRAGraph &G) override {
@@ -421,7 +441,6 @@ public:
// gives the Ok.
for (const auto &MBB : MF) {
for (const auto &MI : MBB) {
-
// Skip not-coalescable or already coalesced copies.
if (!CP.setRegisters(&MI) || CP.getSrcReg() == CP.getDstReg())
continue;
@@ -479,7 +498,6 @@ public:
}
private:
-
void addVirtRegCoalesce(
PBQPRAGraph::RawMatrix &CostMat,
const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed1,
@@ -496,14 +514,15 @@ private:
}
}
}
-
};
-} // End anonymous namespace.
+} // end anonymous namespace
// Out-of-line destructor/anchor for PBQPRAConstraint.
-PBQPRAConstraint::~PBQPRAConstraint() {}
+PBQPRAConstraint::~PBQPRAConstraint() = default;
+
void PBQPRAConstraint::anchor() {}
+
void PBQPRAConstraintList::anchor() {}
void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
@@ -777,7 +796,6 @@ bool RegAllocPBQP::runOnMachineFunction(
// If there are non-empty intervals allocate them using pbqp.
if (!VRegsToAlloc.empty()) {
-
const TargetSubtargetInfo &Subtarget = MF.getSubtarget();
std::unique_ptr<PBQPRAConstraintList> ConstraintsRoot =
llvm::make_unique<PBQPRAConstraintList>();
Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp?rev=295773&r1=295772&r2=295773&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Tue Feb 21 16:07:52 2017
@@ -1,4 +1,4 @@
-//===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===//
+//===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -14,12 +14,21 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/CodeGen/RegisterClassInfo.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RegisterClassInfo.h"
+#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
+#include <algorithm>
+#include <cassert>
+#include <cstdint>
using namespace llvm;
@@ -29,8 +38,7 @@ static cl::opt<unsigned>
StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
cl::desc("Limit all regclasses to N registers"));
-RegisterClassInfo::RegisterClassInfo()
- : Tag(0), MF(nullptr), TRI(nullptr), CalleeSaved(nullptr) {}
+RegisterClassInfo::RegisterClassInfo() = default;
void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
bool Update = false;
@@ -114,7 +122,7 @@ void RegisterClassInfo::compute(const Ta
}
}
RCI.NumRegs = N + CSRAlias.size();
- assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
+ assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
// CSR aliases go after the volatile registers, preserve the target's order.
for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
Modified: llvm/trunk/lib/CodeGen/RegisterPressure.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterPressure.cpp?rev=295773&r1=295772&r2=295773&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterPressure.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterPressure.cpp Tue Feb 21 16:07:52 2017
@@ -1,4 +1,4 @@
-//===-- RegisterPressure.cpp - Dynamic Register Pressure ------------------===//
+//===- RegisterPressure.cpp - Dynamic Register Pressure -------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -12,13 +12,37 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/CodeGen/RegisterPressure.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBundle.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
+#include "llvm/CodeGen/RegisterPressure.h"
+#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/MC/LaneBitmask.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
+#include <algorithm>
+#include <cassert>
+#include <cstdint>
+#include <cstdlib>
+#include <cstring>
+#include <iterator>
+#include <limits>
+#include <utility>
+#include <vector>
using namespace llvm;
@@ -267,7 +291,6 @@ bool RegPressureTracker::isBottomClosed(
MachineBasicBlock::const_iterator());
}
-
SlotIndex RegPressureTracker::getCurrSlot() const {
MachineBasicBlock::const_iterator IdxPos =
skipDebugInstructionsForward(CurrPos, MBB->end());
@@ -331,7 +354,7 @@ void RegPressureTracker::initLiveThru(co
static LaneBitmask getRegLanes(ArrayRef<RegisterMaskPair> RegUnits,
unsigned RegUnit) {
- auto I = find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
+ auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
return Other.RegUnit == RegUnit;
});
if (I == RegUnits.end())
@@ -343,7 +366,7 @@ static void addRegLanes(SmallVectorImpl<
RegisterMaskPair Pair) {
unsigned RegUnit = Pair.RegUnit;
assert(Pair.LaneMask.any());
- auto I = find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
+ auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
return Other.RegUnit == RegUnit;
});
if (I == RegUnits.end()) {
@@ -355,7 +378,7 @@ static void addRegLanes(SmallVectorImpl<
static void setRegZero(SmallVectorImpl<RegisterMaskPair> &RegUnits,
unsigned RegUnit) {
- auto I = find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
+ auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
return Other.RegUnit == RegUnit;
});
if (I == RegUnits.end()) {
@@ -369,7 +392,7 @@ static void removeRegLanes(SmallVectorIm
RegisterMaskPair Pair) {
unsigned RegUnit = Pair.RegUnit;
assert(Pair.LaneMask.any());
- auto I = find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
+ auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
return Other.RegUnit == RegUnit;
});
if (I != RegUnits.end()) {
@@ -426,6 +449,8 @@ namespace {
///
/// FIXME: always ignore tied opers
class RegisterOperandsCollector {
+ friend class llvm::RegisterOperands;
+
RegisterOperands &RegOpers;
const TargetRegisterInfo &TRI;
const MachineRegisterInfo &MRI;
@@ -520,11 +545,9 @@ class RegisterOperandsCollector {
addRegLanes(RegUnits, RegisterMaskPair(*Units, LaneBitmask::getAll()));
}
}
-
- friend class llvm::RegisterOperands;
};
-} // namespace
+} // end anonymous namespace
void RegisterOperands::collect(const MachineInstr &MI,
const TargetRegisterInfo &TRI,
@@ -677,7 +700,7 @@ void RegPressureTracker::discoverLiveInO
assert(Pair.LaneMask.any());
unsigned RegUnit = Pair.RegUnit;
- auto I = find_if(LiveInOrOut, [RegUnit](const RegisterMaskPair &Other) {
+ auto I = llvm::find_if(LiveInOrOut, [RegUnit](const RegisterMaskPair &Other) {
return Other.RegUnit == RegUnit;
});
LaneBitmask PrevMask;
@@ -775,9 +798,10 @@ void RegPressureTracker::recede(const Re
if (!TrackLaneMasks) {
addRegLanes(*LiveUses, RegisterMaskPair(Reg, NewMask));
} else {
- auto I = find_if(*LiveUses, [Reg](const RegisterMaskPair Other) {
- return Other.RegUnit == Reg;
- });
+ auto I =
+ llvm::find_if(*LiveUses, [Reg](const RegisterMaskPair Other) {
+ return Other.RegUnit == Reg;
+ });
bool IsRedef = I != LiveUses->end();
if (IsRedef) {
// ignore re-defs here...
@@ -1157,7 +1181,7 @@ getUpwardPressureDelta(const MachineInst
if (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() == PSetID) {
int CritInc = (int)MNew - (int)CriticalPSets[CritIdx].getUnitInc();
- if (CritInc > 0 && CritInc <= INT16_MAX) {
+ if (CritInc > 0 && CritInc <= std::numeric_limits<int16_t>::max()) {
Delta.CriticalMax = PressureChange(PSetID);
Delta.CriticalMax.setUnitInc(CritInc);
}
Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=295773&r1=295772&r2=295773&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Tue Feb 21 16:07:52 2017
@@ -1,4 +1,4 @@
-//===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
+//===- RegisterScavenging.cpp - Machine register scavenging ---------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -15,18 +15,26 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
+#include <cassert>
+#include <iterator>
+#include <limits>
+#include <string>
+
using namespace llvm;
#define DEBUG_TYPE "reg-scavenging"
@@ -390,7 +398,7 @@ unsigned RegScavenger::scavengeRegister(
unsigned NeedSize = RC->getSize();
unsigned NeedAlign = RC->getAlignment();
- unsigned SI = Scavenged.size(), Diff = UINT_MAX;
+ unsigned SI = Scavenged.size(), Diff = std::numeric_limits<unsigned>::max();
int FIB = MFI.getObjectIndexBegin(), FIE = MFI.getObjectIndexEnd();
for (unsigned I = 0; I < Scavenged.size(); ++I) {
if (Scavenged[I].Reg != 0)
More information about the llvm-commits
mailing list