[llvm] r295736 - [X86][AVX512] Update VPBROADCASTQ test to combine from VPERMQ instead of VPERMI2Q.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Tue Feb 21 11:04:11 2017
New Revision: 295736

URL: http://llvm.org/viewvc/llvm-project?rev=295736&view=rev
Log:
[X86][AVX512] Update VPBROADCASTQ test to combine from VPERMQ instead of VPERMI2Q. 

VPERMI2Q doesn't have shuffle decoding from re-materializable constants.

Modified:
    llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll

Modified: llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll?rev=295736&r1=295735&r2=295736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll Tue Feb 21 11:04:11 2017
@@ -1136,18 +1136,17 @@ define <16 x float> @combine_vpermi2var_
 define <8 x i64> @combine_vpermvar_insertion_as_broadcast_v8i64(i64 %a0) {
 ; X32-LABEL: combine_vpermvar_insertion_as_broadcast_v8i64:
 ; X32:       # BB#0:
-; X32-NEXT:    vmovq {{.*#+}} xmm1 = mem[0],zero
-; X32-NEXT:    vpxord %zmm0, %zmm0, %zmm0
-; X32-NEXT:    vpermi2q %zmm0, %zmm1, %zmm0
+; X32-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero
+; X32-NEXT:    vpxord %zmm1, %zmm1, %zmm1
+; X32-NEXT:    vpermq %zmm0, %zmm1, %zmm0
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: combine_vpermvar_insertion_as_broadcast_v8i64:
 ; X64:       # BB#0:
-; X64-NEXT:    vmovq %rdi, %xmm1
-; X64-NEXT:    vpxord %zmm0, %zmm0, %zmm0
-; X64-NEXT:    vpermi2q %zmm0, %zmm1, %zmm0
+; X64-NEXT:    vmovq %rdi, %xmm0
+; X64-NEXT:    vpbroadcastq %xmm0, %zmm0
 ; X64-NEXT:    retq
   %1 = insertelement <8 x i64> undef, i64 %a0, i32 0
-  %2 = tail call <8 x i64> @llvm.x86.avx512.mask.vpermi2var.q.512(<8 x i64> %1, <8 x i64> zeroinitializer, <8 x i64> undef, i8 -1)
+  %2 = tail call <8 x i64> @llvm.x86.avx512.mask.permvar.di.512(<8 x i64> %1, <8 x i64> zeroinitializer, <8 x i64> undef, i8 -1)
   ret <8 x i64> %2
 }