[PATCH] D29489: Optimize SETCC + VSEL of incompatible or illegal types

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a subscriber: spatel.
RKSimon added a comment.

In https://reviews.llvm.org/D29489#681999, @jonpa wrote:

> I got regressions on several targets when applying this. I could eliminate a few by adding more checks before transformation. Left are target tests that I can't really judge if things have improved for that target and if so the test should be updated, or if the patch is flawed. These are failing with the patch as it is:
>
>   LLVM :: CodeGen/ARM/vuzp.ll
>   LLVM :: CodeGen/X86/2011-10-19-widen_vselect.ll
>   LLVM :: CodeGen/X86/2011-10-21-widen-cmp.ll
>   LLVM :: CodeGen/X86/psubus.ll


>From a local build I've just ran all those regressions (remove unnecessary sign manipulations) look like improvements to me! Please can you include them to show the deltas, all of them can be regenerated by running llvm\utils\update_llc_test_checks.py

> To be honest, at the moment this method is working well basically under the assumptions of the SystemZ target, which for one thing only has vector registers of 128 bits. It also has its way of using a vector register as a bitmask to perform vector selects, and I am not sure if other targets do this the same way. So I would actually suggest that I move this to a custom lowering for SystemZ of VSELECT instead for now. Unless of course this is also a known issue on some other target, and somebody wants to jump in and help me finish the patch right away.

You at least need to add some SystemZ specific tests before making that decision but nothing I've seen so far makes me think it has to be target specific.

> It would have been nice to just improve common code by improving DAGCombines of SEXT_INREG etc, but after trying all of that, it turns out that in order to handle all the cases, it is really preferred to do it early before it gets scalarized.

Can you give some examples of the patterns that we're missing? I'm trying to improve combining *_EXTEND_VECTOR_INREG instructions which probably has a lot of crossover.


https://reviews.llvm.org/D29489