[llvm] r295707 - [X86] Remove sse4.2 intrinsic tests from the avx intrinsics test file. Fix some other consistency issues.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 21 00:06:06 PST 2017
Author: ctopper
Date: Tue Feb 21 02:06:05 2017
New Revision: 295707
URL: http://llvm.org/viewvc/llvm-project?rev=295707&view=rev
Log:
[X86] Remove sse4.2 intrinsic tests from the avx intrinsics test file. Fix some other consistency issues.
They are all covered by the SSE4.2 intrinsics test with SSE4.2, AVX, and AVX512 command lines.
Merge sse42.ll into the other intrinsics test. Rename sse42_64.ll to be named like other intrinsic tests.
Added:
llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86_64.ll
Removed:
llvm/trunk/test/CodeGen/X86/sse42.ll
llvm/trunk/test/CodeGen/X86/sse42_64.ll
Modified:
llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll
llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86.ll
Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=295707&r1=295706&r2=295707&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Tue Feb 21 02:06:05 2017
@@ -1,289 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=avx,aes,pclmul -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=avx,pclmul -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=skx -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL
-define i32 @test_x86_sse42_pcmpestri128(<16 x i8> %a0, <16 x i8> %a2) {
-; CHECK-LABEL: test_x86_sse42_pcmpestri128:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
-; CHECK-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
-; CHECK-NEXT: movl %ecx, %eax ## encoding: [0x89,0xc8]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %res = call i32 @llvm.x86.sse42.pcmpestri128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
- ret i32 %res
-}
-declare i32 @llvm.x86.sse42.pcmpestri128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
-
-
-define i32 @test_x86_sse42_pcmpestri128_load(<16 x i8>* %a0, <16 x i8>* %a2) {
-; AVX-LABEL: test_x86_sse42_pcmpestri128_load:
-; AVX: ## BB#0:
-; AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x08]
-; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; AVX-NEXT: vmovdqa (%eax), %xmm0 ## encoding: [0xc5,0xf9,0x6f,0x00]
-; AVX-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
-; AVX-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; AVX-NEXT: vpcmpestri $7, (%ecx), %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0x01,0x07]
-; AVX-NEXT: movl %ecx, %eax ## encoding: [0x89,0xc8]
-; AVX-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_sse42_pcmpestri128_load:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x08]
-; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; AVX512VL-NEXT: vmovdqu (%eax), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x6f,0x00]
-; AVX512VL-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
-; AVX512VL-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; AVX512VL-NEXT: vpcmpestri $7, (%ecx), %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0x01,0x07]
-; AVX512VL-NEXT: movl %ecx, %eax ## encoding: [0x89,0xc8]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
- %1 = load <16 x i8>, <16 x i8>* %a0
- %2 = load <16 x i8>, <16 x i8>* %a2
- %res = call i32 @llvm.x86.sse42.pcmpestri128(<16 x i8> %1, i32 7, <16 x i8> %2, i32 7, i8 7) ; <i32> [#uses=1]
- ret i32 %res
-}
-
-
-define i32 @test_x86_sse42_pcmpestria128(<16 x i8> %a0, <16 x i8> %a2) nounwind {
-; CHECK-LABEL: test_x86_sse42_pcmpestria128:
-; CHECK: ## BB#0:
-; CHECK-NEXT: pushl %ebx ## encoding: [0x53]
-; CHECK-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
-; CHECK-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; CHECK-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
-; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
-; CHECK-NEXT: seta %bl ## encoding: [0x0f,0x97,0xc3]
-; CHECK-NEXT: movl %ebx, %eax ## encoding: [0x89,0xd8]
-; CHECK-NEXT: popl %ebx ## encoding: [0x5b]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %res = call i32 @llvm.x86.sse42.pcmpestria128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
- ret i32 %res
-}
-declare i32 @llvm.x86.sse42.pcmpestria128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
-
-
-define i32 @test_x86_sse42_pcmpestric128(<16 x i8> %a0, <16 x i8> %a2) {
-; CHECK-LABEL: test_x86_sse42_pcmpestric128:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
-; CHECK-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
-; CHECK-NEXT: sbbl %eax, %eax ## encoding: [0x19,0xc0]
-; CHECK-NEXT: andl $1, %eax ## encoding: [0x83,0xe0,0x01]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %res = call i32 @llvm.x86.sse42.pcmpestric128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
- ret i32 %res
-}
-declare i32 @llvm.x86.sse42.pcmpestric128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
-
-
-define i32 @test_x86_sse42_pcmpestrio128(<16 x i8> %a0, <16 x i8> %a2) nounwind {
-; CHECK-LABEL: test_x86_sse42_pcmpestrio128:
-; CHECK: ## BB#0:
-; CHECK-NEXT: pushl %ebx ## encoding: [0x53]
-; CHECK-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
-; CHECK-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; CHECK-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
-; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
-; CHECK-NEXT: seto %bl ## encoding: [0x0f,0x90,0xc3]
-; CHECK-NEXT: movl %ebx, %eax ## encoding: [0x89,0xd8]
-; CHECK-NEXT: popl %ebx ## encoding: [0x5b]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %res = call i32 @llvm.x86.sse42.pcmpestrio128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
- ret i32 %res
-}
-declare i32 @llvm.x86.sse42.pcmpestrio128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
-
-
-define i32 @test_x86_sse42_pcmpestris128(<16 x i8> %a0, <16 x i8> %a2) nounwind {
-; CHECK-LABEL: test_x86_sse42_pcmpestris128:
-; CHECK: ## BB#0:
-; CHECK-NEXT: pushl %ebx ## encoding: [0x53]
-; CHECK-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
-; CHECK-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; CHECK-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
-; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
-; CHECK-NEXT: sets %bl ## encoding: [0x0f,0x98,0xc3]
-; CHECK-NEXT: movl %ebx, %eax ## encoding: [0x89,0xd8]
-; CHECK-NEXT: popl %ebx ## encoding: [0x5b]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %res = call i32 @llvm.x86.sse42.pcmpestris128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
- ret i32 %res
-}
-declare i32 @llvm.x86.sse42.pcmpestris128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
-
-
-define i32 @test_x86_sse42_pcmpestriz128(<16 x i8> %a0, <16 x i8> %a2) nounwind {
-; CHECK-LABEL: test_x86_sse42_pcmpestriz128:
-; CHECK: ## BB#0:
-; CHECK-NEXT: pushl %ebx ## encoding: [0x53]
-; CHECK-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
-; CHECK-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; CHECK-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
-; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
-; CHECK-NEXT: sete %bl ## encoding: [0x0f,0x94,0xc3]
-; CHECK-NEXT: movl %ebx, %eax ## encoding: [0x89,0xd8]
-; CHECK-NEXT: popl %ebx ## encoding: [0x5b]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %res = call i32 @llvm.x86.sse42.pcmpestriz128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
- ret i32 %res
-}
-declare i32 @llvm.x86.sse42.pcmpestriz128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
-
-
-define <16 x i8> @test_x86_sse42_pcmpestrm128(<16 x i8> %a0, <16 x i8> %a2) {
-; CHECK-LABEL: test_x86_sse42_pcmpestrm128:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
-; CHECK-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; CHECK-NEXT: vpcmpestrm $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x60,0xc1,0x07]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %res = call <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <<16 x i8>> [#uses=1]
- ret <16 x i8> %res
-}
-declare <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
-
-
-define <16 x i8> @test_x86_sse42_pcmpestrm128_load(<16 x i8> %a0, <16 x i8>* %a2) {
-; CHECK-LABEL: test_x86_sse42_pcmpestrm128_load:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x04]
-; CHECK-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
-; CHECK-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; CHECK-NEXT: vpcmpestrm $7, (%ecx), %xmm0 ## encoding: [0xc4,0xe3,0x79,0x60,0x01,0x07]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %1 = load <16 x i8>, <16 x i8>* %a2
- %res = call <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8> %a0, i32 7, <16 x i8> %1, i32 7, i8 7) ; <<16 x i8>> [#uses=1]
- ret <16 x i8> %res
-}
-
-
-define i32 @test_x86_sse42_pcmpistri128(<16 x i8> %a0, <16 x i8> %a1) {
-; CHECK-LABEL: test_x86_sse42_pcmpistri128:
-; CHECK: ## BB#0:
-; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x63,0xc1,0x07]
-; CHECK-NEXT: movl %ecx, %eax ## encoding: [0x89,0xc8]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %res = call i32 @llvm.x86.sse42.pcmpistri128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
- ret i32 %res
-}
-declare i32 @llvm.x86.sse42.pcmpistri128(<16 x i8>, <16 x i8>, i8) nounwind readnone
-
-
-define i32 @test_x86_sse42_pcmpistri128_load(<16 x i8>* %a0, <16 x i8>* %a1) {
-; AVX-LABEL: test_x86_sse42_pcmpistri128_load:
-; AVX: ## BB#0:
-; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08]
-; AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x04]
-; AVX-NEXT: vmovdqa (%ecx), %xmm0 ## encoding: [0xc5,0xf9,0x6f,0x01]
-; AVX-NEXT: vpcmpistri $7, (%eax), %xmm0 ## encoding: [0xc4,0xe3,0x79,0x63,0x00,0x07]
-; AVX-NEXT: movl %ecx, %eax ## encoding: [0x89,0xc8]
-; AVX-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_sse42_pcmpistri128_load:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08]
-; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x04]
-; AVX512VL-NEXT: vmovdqu (%ecx), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x6f,0x01]
-; AVX512VL-NEXT: vpcmpistri $7, (%eax), %xmm0 ## encoding: [0xc4,0xe3,0x79,0x63,0x00,0x07]
-; AVX512VL-NEXT: movl %ecx, %eax ## encoding: [0x89,0xc8]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
- %1 = load <16 x i8>, <16 x i8>* %a0
- %2 = load <16 x i8>, <16 x i8>* %a1
- %res = call i32 @llvm.x86.sse42.pcmpistri128(<16 x i8> %1, <16 x i8> %2, i8 7) ; <i32> [#uses=1]
- ret i32 %res
-}
-
-
-define i32 @test_x86_sse42_pcmpistria128(<16 x i8> %a0, <16 x i8> %a1) {
-; CHECK-LABEL: test_x86_sse42_pcmpistria128:
-; CHECK: ## BB#0:
-; CHECK-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
-; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x63,0xc1,0x07]
-; CHECK-NEXT: seta %al ## encoding: [0x0f,0x97,0xc0]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %res = call i32 @llvm.x86.sse42.pcmpistria128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
- ret i32 %res
-}
-declare i32 @llvm.x86.sse42.pcmpistria128(<16 x i8>, <16 x i8>, i8) nounwind readnone
-
-
-define i32 @test_x86_sse42_pcmpistric128(<16 x i8> %a0, <16 x i8> %a1) {
-; CHECK-LABEL: test_x86_sse42_pcmpistric128:
-; CHECK: ## BB#0:
-; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x63,0xc1,0x07]
-; CHECK-NEXT: sbbl %eax, %eax ## encoding: [0x19,0xc0]
-; CHECK-NEXT: andl $1, %eax ## encoding: [0x83,0xe0,0x01]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %res = call i32 @llvm.x86.sse42.pcmpistric128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
- ret i32 %res
-}
-declare i32 @llvm.x86.sse42.pcmpistric128(<16 x i8>, <16 x i8>, i8) nounwind readnone
-
-
-define i32 @test_x86_sse42_pcmpistrio128(<16 x i8> %a0, <16 x i8> %a1) {
-; CHECK-LABEL: test_x86_sse42_pcmpistrio128:
-; CHECK: ## BB#0:
-; CHECK-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
-; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x63,0xc1,0x07]
-; CHECK-NEXT: seto %al ## encoding: [0x0f,0x90,0xc0]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %res = call i32 @llvm.x86.sse42.pcmpistrio128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
- ret i32 %res
-}
-declare i32 @llvm.x86.sse42.pcmpistrio128(<16 x i8>, <16 x i8>, i8) nounwind readnone
-
-
-define i32 @test_x86_sse42_pcmpistris128(<16 x i8> %a0, <16 x i8> %a1) {
-; CHECK-LABEL: test_x86_sse42_pcmpistris128:
-; CHECK: ## BB#0:
-; CHECK-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
-; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x63,0xc1,0x07]
-; CHECK-NEXT: sets %al ## encoding: [0x0f,0x98,0xc0]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %res = call i32 @llvm.x86.sse42.pcmpistris128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
- ret i32 %res
-}
-declare i32 @llvm.x86.sse42.pcmpistris128(<16 x i8>, <16 x i8>, i8) nounwind readnone
-
-
-define i32 @test_x86_sse42_pcmpistriz128(<16 x i8> %a0, <16 x i8> %a1) {
-; CHECK-LABEL: test_x86_sse42_pcmpistriz128:
-; CHECK: ## BB#0:
-; CHECK-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
-; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x63,0xc1,0x07]
-; CHECK-NEXT: sete %al ## encoding: [0x0f,0x94,0xc0]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %res = call i32 @llvm.x86.sse42.pcmpistriz128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
- ret i32 %res
-}
-declare i32 @llvm.x86.sse42.pcmpistriz128(<16 x i8>, <16 x i8>, i8) nounwind readnone
-
-
-define <16 x i8> @test_x86_sse42_pcmpistrm128(<16 x i8> %a0, <16 x i8> %a1) {
-; CHECK-LABEL: test_x86_sse42_pcmpistrm128:
-; CHECK: ## BB#0:
-; CHECK-NEXT: vpcmpistrm $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x62,0xc1,0x07]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %res = call <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <<16 x i8>> [#uses=1]
- ret <16 x i8> %res
-}
-declare <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8>, <16 x i8>, i8) nounwind readnone
-
-
-define <16 x i8> @test_x86_sse42_pcmpistrm128_load(<16 x i8> %a0, <16 x i8>* %a1) {
-; CHECK-LABEL: test_x86_sse42_pcmpistrm128_load:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpcmpistrm $7, (%eax), %xmm0 ## encoding: [0xc4,0xe3,0x79,0x62,0x00,0x07]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %1 = load <16 x i8>, <16 x i8>* %a1
- %res = call <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8> %a0, <16 x i8> %1, i8 7) ; <<16 x i8>> [#uses=1]
- ret <16 x i8> %res
-}
-
-
define <16 x i8> @test_x86_ssse3_pabs_b_128(<16 x i8> %a0) {
; AVX-LABEL: test_x86_ssse3_pabs_b_128:
; AVX: ## BB#0:
@@ -1506,45 +1224,12 @@ define void @test_x86_avx_vzeroupper() {
}
declare void @llvm.x86.avx.vzeroupper() nounwind
-define i32 @crc32_32_8(i32 %a, i8 %b) nounwind {
-; CHECK-LABEL: crc32_32_8:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: crc32b {{[0-9]+}}(%esp), %eax ## encoding: [0xf2,0x0f,0x38,0xf0,0x44,0x24,0x08]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b)
- ret i32 %tmp
-}
-declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind
-
-define i32 @crc32_32_16(i32 %a, i16 %b) nounwind {
-; CHECK-LABEL: crc32_32_16:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: crc32w {{[0-9]+}}(%esp), %eax ## encoding: [0x66,0xf2,0x0f,0x38,0xf1,0x44,0x24,0x08]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %tmp = call i32 @llvm.x86.sse42.crc32.32.16(i32 %a, i16 %b)
- ret i32 %tmp
-}
-declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind
-
-define i32 @crc32_32_32(i32 %a, i32 %b) nounwind {
-; CHECK-LABEL: crc32_32_32:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: crc32l {{[0-9]+}}(%esp), %eax ## encoding: [0xf2,0x0f,0x38,0xf1,0x44,0x24,0x08]
-; CHECK-NEXT: retl ## encoding: [0xc3]
- %tmp = call i32 @llvm.x86.sse42.crc32.32.32(i32 %a, i32 %b)
- ret i32 %tmp
-}
-declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind
-
define void @movnt_dq(i8* %p, <2 x i64> %a1) nounwind {
; AVX-LABEL: movnt_dq:
; AVX: ## BB#0:
; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; AVX-NEXT: vpaddq LCPI102_0, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xd4,0x05,A,A,A,A]
-; AVX-NEXT: ## fixup A - offset: 4, value: LCPI102_0, kind: FK_Data_4
+; AVX-NEXT: vpaddq LCPI81_0, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xd4,0x05,A,A,A,A]
+; AVX-NEXT: ## fixup A - offset: 4, value: LCPI81_0, kind: FK_Data_4
; AVX-NEXT: vmovntdq %ymm0, (%eax) ## encoding: [0xc5,0xfd,0xe7,0x00]
; AVX-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; AVX-NEXT: retl ## encoding: [0xc3]
@@ -1552,8 +1237,8 @@ define void @movnt_dq(i8* %p, <2 x i64>
; AVX512VL-LABEL: movnt_dq:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; AVX512VL-NEXT: vpaddq LCPI102_0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xd4,0x05,A,A,A,A]
-; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI102_0, kind: FK_Data_4
+; AVX512VL-NEXT: vpaddq LCPI81_0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xd4,0x05,A,A,A,A]
+; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI81_0, kind: FK_Data_4
; AVX512VL-NEXT: vmovntdq %ymm0, (%eax) ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe7,0x00]
; AVX512VL-NEXT: retl ## encoding: [0xc3]
%a2 = add <2 x i64> %a1, <i64 1, i64 1>
Modified: llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86.ll?rev=295707&r1=295706&r2=295707&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86.ll Tue Feb 21 02:06:05 2017
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=-avx,+sse4.2 -show-mc-encoding | FileCheck %s --check-prefix=SSE42
-; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+avx2 -show-mc-encoding | FileCheck %s --check-prefix=VCHECK --check-prefix=AVX2
-; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=skx -show-mc-encoding | FileCheck %s --check-prefix=VCHECK --check-prefix=SKX
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=-avx,+sse4.2 -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=SSE42
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+avx2 -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=VCHECK --check-prefix=AVX2
+; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=skx -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=VCHECK --check-prefix=SKX
define i32 @test_x86_sse42_pcmpestri128(<16 x i8> %a0, <16 x i8> %a2) {
; SSE42-LABEL: test_x86_sse42_pcmpestri128:
@@ -435,3 +435,36 @@ define <16 x i8> @test_x86_sse42_pcmpist
%res = call <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8> %a0, <16 x i8> %1, i8 7) ; <<16 x i8>> [#uses=1]
ret <16 x i8> %res
}
+
+define i32 @crc32_32_8(i32 %a, i8 %b) nounwind {
+; CHECK-LABEL: crc32_32_8:
+; CHECK: ## BB#0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; CHECK-NEXT: crc32b {{[0-9]+}}(%esp), %eax ## encoding: [0xf2,0x0f,0x38,0xf0,0x44,0x24,0x08]
+; CHECK-NEXT: retl ## encoding: [0xc3]
+ %tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b)
+ ret i32 %tmp
+}
+declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind
+
+define i32 @crc32_32_16(i32 %a, i16 %b) nounwind {
+; CHECK-LABEL: crc32_32_16:
+; CHECK: ## BB#0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; CHECK-NEXT: crc32w {{[0-9]+}}(%esp), %eax ## encoding: [0x66,0xf2,0x0f,0x38,0xf1,0x44,0x24,0x08]
+; CHECK-NEXT: retl ## encoding: [0xc3]
+ %tmp = call i32 @llvm.x86.sse42.crc32.32.16(i32 %a, i16 %b)
+ ret i32 %tmp
+}
+declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind
+
+define i32 @crc32_32_32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc32_32_32:
+; CHECK: ## BB#0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; CHECK-NEXT: crc32l {{[0-9]+}}(%esp), %eax ## encoding: [0xf2,0x0f,0x38,0xf1,0x44,0x24,0x08]
+; CHECK-NEXT: retl ## encoding: [0xc3]
+ %tmp = call i32 @llvm.x86.sse42.crc32.32.32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind
Added: llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86_64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86_64.ll?rev=295707&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86_64.ll (added)
+++ llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86_64.ll Tue Feb 21 02:06:05 2017
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse4.2 -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=SSE42
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx2 -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=VCHECK --check-prefix=AVX2
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=VCHECK --check-prefix=SKX
+
+declare i64 @llvm.x86.sse42.crc32.64.8(i64, i8) nounwind
+declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind
+
+define i64 @crc32_64_8(i64 %a, i8 %b) nounwind {
+; CHECK-LABEL: crc32_64_8:
+; CHECK: ## BB#0:
+; CHECK-NEXT: crc32b %sil, %edi ## encoding: [0xf2,0x40,0x0f,0x38,0xf0,0xfe]
+; CHECK-NEXT: movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %tmp = call i64 @llvm.x86.sse42.crc32.64.8(i64 %a, i8 %b)
+ ret i64 %tmp
+}
+
+define i64 @crc32_64_64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: crc32_64_64:
+; CHECK: ## BB#0:
+; CHECK-NEXT: crc32q %rsi, %rdi ## encoding: [0xf2,0x48,0x0f,0x38,0xf1,0xfe]
+; CHECK-NEXT: movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %tmp = call i64 @llvm.x86.sse42.crc32.64.64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
Removed: llvm/trunk/test/CodeGen/X86/sse42.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse42.ll?rev=295706&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse42.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse42.ll (removed)
@@ -1,58 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4.2 | FileCheck %s --check-prefix=X32
-; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse4.2 | FileCheck %s --check-prefix=X64
-
-declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind
-declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind
-declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind
-
-define i32 @crc32_32_8(i32 %a, i8 %b) nounwind {
-; X32-LABEL: crc32_32_8:
-; X32: ## BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: crc32b {{[0-9]+}}(%esp), %eax
-; X32-NEXT: retl
-;
-; X64-LABEL: crc32_32_8:
-; X64: ## BB#0:
-; X64-NEXT: crc32b %sil, %edi
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: retq
- %tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b)
- ret i32 %tmp
-}
-
-
-define i32 @crc32_32_16(i32 %a, i16 %b) nounwind {
-; X32-LABEL: crc32_32_16:
-; X32: ## BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: crc32w {{[0-9]+}}(%esp), %eax
-; X32-NEXT: retl
-;
-; X64-LABEL: crc32_32_16:
-; X64: ## BB#0:
-; X64-NEXT: crc32w %si, %edi
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: retq
- %tmp = call i32 @llvm.x86.sse42.crc32.32.16(i32 %a, i16 %b)
- ret i32 %tmp
-}
-
-
-define i32 @crc32_32_32(i32 %a, i32 %b) nounwind {
-; X32-LABEL: crc32_32_32:
-; X32: ## BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: crc32l {{[0-9]+}}(%esp), %eax
-; X32-NEXT: retl
-;
-; X64-LABEL: crc32_32_32:
-; X64: ## BB#0:
-; X64-NEXT: crc32l %esi, %edi
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: retq
- %tmp = call i32 @llvm.x86.sse42.crc32.32.32(i32 %a, i32 %b)
- ret i32 %tmp
-}
-
Removed: llvm/trunk/test/CodeGen/X86/sse42_64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse42_64.ll?rev=295706&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse42_64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse42_64.ll (removed)
@@ -1,21 +0,0 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse4.2 | FileCheck %s -check-prefix=X64
-
-declare i64 @llvm.x86.sse42.crc32.64.8(i64, i8) nounwind
-declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind
-
-define i64 @crc32_64_8(i64 %a, i8 %b) nounwind {
- %tmp = call i64 @llvm.x86.sse42.crc32.64.8(i64 %a, i8 %b)
- ret i64 %tmp
-
-; X64: _crc32_64_8:
-; X64: crc32b %sil,
-}
-
-define i64 @crc32_64_64(i64 %a, i64 %b) nounwind {
- %tmp = call i64 @llvm.x86.sse42.crc32.64.64(i64 %a, i64 %b)
- ret i64 %tmp
-
-; X64: _crc32_64_64:
-; X64: crc32q %rsi,
-}
-
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