[PATCH] D30180: [DAGCombiner] add missing folds for scalar select of {-1, 0, 1}

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
Herald added subscribers: tpr, nhaehnle, wdng, nemanjai, mcrosier.

I think all of the test changes here are wins or neutral, but anyone who knows AMDGPU, Hexagon, and NVPTX should take a look at those diffs. If it makes it easier, I can post the full before/after asm of the affected tests for those targets.

The motivation for filling out these select-of-constants cases goes back to https://reviews.llvm.org/D24480, where we discussed removing an IR fold from add(zext) --> select. And that goes back to:
https://reviews.llvm.org/rL75531
https://reviews.llvm.org/rL159230

The idea is that we should always canonicalize patterns like this to a select-of-constants in IR because that's the smallest IR and the best for value tracking. Note that we currently do the opposite in some cases (like the cases in *this* patch). Ie, the proposed folds in this patch already exist in InstCombine today:
https://github.com/llvm-mirror/llvm/blob/master/lib/Transforms/InstCombine/InstCombineSelect.cpp#L1151

As this patch shows, most targets generate better machine code for simple ext/add/not ops rather than a select of constants. So the follow-up steps to make this less of a patchwork of special-case folds and missing IR canonicalization:

1. Have DAGCombiner convert any select of constants into ext/add/not ops.
2. Have InstCombine canonicalize in the other direction (create more selects).


https://reviews.llvm.org/D30180

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AMDGPU/trunc.ll
  test/CodeGen/ARM/select_const.ll
  test/CodeGen/Hexagon/adde.ll
  test/CodeGen/Hexagon/sube.ll
  test/CodeGen/NVPTX/add-128bit.ll
  test/CodeGen/PowerPC/select_const.ll
  test/CodeGen/X86/select_const.ll

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