[llvm] r295665 - [X86][SSE] Regenerate vselect widening tests and add 32-bit test target

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Mon Feb 20 09:16:43 2017
New Revision: 295665

URL: http://llvm.org/viewvc/llvm-project?rev=295665&view=rev
Log:
[X86][SSE] Regenerate vselect widening tests and add 32-bit test target

Modified:
    llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll

Modified: llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll?rev=295665&r1=295664&r2=295665&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll Mon Feb 20 09:16:43 2017
@@ -1,23 +1,50 @@
-; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -mcpu=corei7   | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s --check-prefix=X64
 
 ; Make sure that we don't crash when legalizing vselect and vsetcc and that
 ; we are able to generate vector blend instructions.
 
-; CHECK-LABEL: simple_widen
-; CHECK-NOT: blend
-; CHECK: ret
 define void @simple_widen(<2 x float> %a, <2 x float> %b) {
+; X32-LABEL: simple_widen:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    extractps $1, %xmm1, (%eax)
+; X32-NEXT:    movss %xmm1, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: simple_widen:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movlps %xmm1, (%rax)
+; X64-NEXT:    retq
 entry:
   %0 = select <2 x i1> undef, <2 x float> %a, <2 x float> %b
   store <2 x float> %0, <2 x float>* undef
   ret void
 }
 
-; CHECK-LABEL: complex_inreg_work
-; CHECK: blend
-; CHECK: ret
-
 define void @complex_inreg_work(<2 x float> %a, <2 x float> %b) {
+; X32-LABEL: complex_inreg_work:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movaps %xmm0, %xmm2
+; X32-NEXT:    cmpordps %xmm0, %xmm0
+; X32-NEXT:    pmovsxdq %xmm0, %xmm0
+; X32-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; X32-NEXT:    pslld $31, %xmm0
+; X32-NEXT:    blendvps %xmm0, %xmm2, %xmm1
+; X32-NEXT:    extractps $1, %xmm1, (%eax)
+; X32-NEXT:    movss %xmm1, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: complex_inreg_work:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movaps %xmm0, %xmm2
+; X64-NEXT:    cmpordps %xmm0, %xmm0
+; X64-NEXT:    pmovsxdq %xmm0, %xmm0
+; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; X64-NEXT:    pslld $31, %xmm0
+; X64-NEXT:    blendvps %xmm0, %xmm2, %xmm1
+; X64-NEXT:    movlps %xmm1, (%rax)
+; X64-NEXT:    retq
 entry:
   %0 = fcmp oeq <2 x float> undef, undef
   %1 = select <2 x i1> %0, <2 x float> %a, <2 x float> %b
@@ -25,22 +52,70 @@ entry:
   ret void
 }
 
-; CHECK-LABEL: zero_test
-; CHECK: xorps %xmm0, %xmm0
-; CHECK: ret
-
 define void @zero_test() {
+; X32-LABEL: zero_test:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    pxor %xmm0, %xmm0
+; X32-NEXT:    pextrd $1, %xmm0, (%eax)
+; X32-NEXT:    movd %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: zero_test:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    xorps %xmm0, %xmm0
+; X64-NEXT:    movlps %xmm0, (%rax)
+; X64-NEXT:    retq
 entry:
   %0 = select <2 x i1> undef, <2 x float> undef, <2 x float> zeroinitializer
   store <2 x float> %0, <2 x float>* undef
   ret void
 }
 
-; CHECK-LABEL: full_test
-; CHECK: blend
-; CHECK: ret
-
 define void @full_test() {
+; X32-LABEL: full_test:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    subl $60, %esp
+; X32-NEXT:  .Lcfi0:
+; X32-NEXT:    .cfi_def_cfa_offset 64
+; X32-NEXT:    movsd {{.*#+}} xmm2 = mem[0],zero
+; X32-NEXT:    cvttps2dq %xmm2, %xmm0
+; X32-NEXT:    cvtdq2ps %xmm0, %xmm1
+; X32-NEXT:    xorps %xmm0, %xmm0
+; X32-NEXT:    cmpltps %xmm2, %xmm0
+; X32-NEXT:    pmovsxdq %xmm0, %xmm0
+; X32-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; X32-NEXT:    pslld $31, %xmm0
+; X32-NEXT:    movaps {{.*#+}} xmm3 = <1,1,u,u>
+; X32-NEXT:    addps %xmm1, %xmm3
+; X32-NEXT:    movaps %xmm1, %xmm4
+; X32-NEXT:    blendvps %xmm0, %xmm3, %xmm4
+; X32-NEXT:    cmpeqps %xmm2, %xmm1
+; X32-NEXT:    movaps %xmm1, %xmm0
+; X32-NEXT:    blendvps %xmm0, %xmm2, %xmm4
+; X32-NEXT:    extractps $1, %xmm4, {{[0-9]+}}(%esp)
+; X32-NEXT:    movss %xmm4, {{[0-9]+}}(%esp)
+; X32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; X32-NEXT:    movsd %xmm0, {{[0-9]+}}(%esp)
+; X32-NEXT:    addl $60, %esp
+; X32-NEXT:    retl
+;
+; X64-LABEL: full_test:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movsd {{.*#+}} xmm2 = mem[0],zero
+; X64-NEXT:    cvttps2dq %xmm2, %xmm0
+; X64-NEXT:    cvtdq2ps %xmm0, %xmm1
+; X64-NEXT:    xorps %xmm0, %xmm0
+; X64-NEXT:    cmpltps %xmm2, %xmm0
+; X64-NEXT:    movaps {{.*#+}} xmm3 = <1,1,u,u>
+; X64-NEXT:    addps %xmm1, %xmm3
+; X64-NEXT:    movaps %xmm1, %xmm4
+; X64-NEXT:    blendvps %xmm0, %xmm3, %xmm4
+; X64-NEXT:    cmpeqps %xmm2, %xmm1
+; X64-NEXT:    movaps %xmm1, %xmm0
+; X64-NEXT:    blendvps %xmm0, %xmm2, %xmm4
+; X64-NEXT:    movlps %xmm4, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movlps %xmm4, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    retq
  entry:
    %Cy300 = alloca <4 x float>
    %Cy11a = alloca <2 x float>
@@ -62,5 +137,3 @@ define void @full_test() {
    store <2 x float> %8, <2 x float>* %Cy11a
    ret void
 }
-
-