[llvm] r295555 - AMDGPU: Fix disassembly of aperture registers

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Sat Feb 18 12:41:41 2017
New Revision: 295555

URL: http://llvm.org/viewvc/llvm-project?rev=295555&view=rev
Log:
AMDGPU: Fix disassembly of aperture registers

Added:
    llvm/trunk/test/MC/Disassembler/AMDGPU/aperture-regs.ll
Modified:
    llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp?rev=295555&r1=295554&r2=295555&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp Sat Feb 18 12:41:41 2017
@@ -523,6 +523,11 @@ MCOperand AMDGPUDisassembler::decodeSpec
   case 124: return createRegOperand(M0);
   case 126: return createRegOperand(EXEC_LO);
   case 127: return createRegOperand(EXEC_HI);
+  case 235: return createRegOperand(SRC_SHARED_BASE);
+  case 236: return createRegOperand(SRC_SHARED_LIMIT);
+  case 237: return createRegOperand(SRC_PRIVATE_BASE);
+  case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
+    // TODO: SRC_POPS_EXITING_WAVE_ID
     // ToDo: no support for vccz register
   case 251: break;
     // ToDo: no support for execz register

Added: llvm/trunk/test/MC/Disassembler/AMDGPU/aperture-regs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/aperture-regs.ll?rev=295555&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/aperture-regs.ll (added)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/aperture-regs.ll Sat Feb 18 12:41:41 2017
@@ -0,0 +1,13 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX9 %s
+
+# GFX9: v_mov_b32_e32 v1, src_shared_base ; encoding: [0xeb,0x02,0x02,0x7e]
+0xeb 0x02 0x02 0x7e
+
+# GFX9: v_mov_b32_e32 v1, src_shared_limit ; encoding: [0xec,0x02,0x02,0x7e]
+0xec 0x02 0x02 0x7e
+
+# GFX9: v_mov_b32_e32 v1, src_private_base ; encoding: [0xed,0x02,0x02,0x7e]
+0xed 0x02 0x02 0x7e
+
+# GFX9: v_mov_b32_e32 v1, src_private_limit ; encoding: [0xee,0x02,0x02,0x7e]
+0xee 0x02 0x02 0x7e