[llvm] r295476 - GlobalISel: verify that generic loads & stores have a mem operand.
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 17 10:50:15 PST 2017
Author: tnorthover
Date: Fri Feb 17 12:50:15 2017
New Revision: 295476
URL: http://llvm.org/viewvc/llvm-project?rev=295476&view=rev
Log:
GlobalISel: verify that generic loads & stores have a mem operand.
The mem operand is used by GlobalISel to convey atomic constraints so dropping
it is invalid.
Modified:
llvm/trunk/lib/CodeGen/MachineVerifier.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=295476&r1=295475&r2=295476&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Fri Feb 17 12:50:15 2017
@@ -908,6 +908,14 @@ void MachineVerifier::visitMachineInstrB
}
}
+ // Generic loads and stores must have a single MachineMemOperand
+ // describing that access.
+ if ((MI->getOpcode() == TargetOpcode::G_LOAD ||
+ MI->getOpcode() == TargetOpcode::G_STORE) &&
+ !MI->hasOneMemOperand())
+ report("Generic instruction accessing memory must have one mem operand",
+ MI);
+
StringRef ErrorInfo;
if (!TII->verifyInstruction(*MI, ErrorInfo))
report(ErrorInfo.data(), MI);
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir?rev=295476&r1=295475&r2=295476&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir Fri Feb 17 12:50:15 2017
@@ -622,7 +622,7 @@ body: |
; CHECK: %0(p0) = COPY %x0
; CHECK: %1(s32) = G_LOAD %0
%0(p0) = COPY %x0
- %1(s32) = G_LOAD %0
+ %1(s32) = G_LOAD %0 :: (load 4)
...
---
@@ -643,7 +643,7 @@ body: |
; CHECK: G_STORE %1(s32), %0(p0)
%0(p0) = COPY %x0
%1(s32) = COPY %w1
- G_STORE %1, %0
+ G_STORE %1, %0 :: (store 4)
...
---
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=295476&r1=295475&r2=295476&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Fri Feb 17 12:50:15 2017
@@ -320,13 +320,13 @@ body: |
%0(p0) = G_FRAME_INDEX %fixed-stack.2
; CHECK: [[FI32VREG:%[0-9]+]] = ADDri %fixed-stack.[[FI32]], 0, 14, _, _
- %1(s32) = G_LOAD %0(p0)
+ %1(s32) = G_LOAD %0(p0) :: (load 4)
; CHECK: {{%[0-9]+}} = LDRi12 [[FI32VREG]], 0, 14, _
%2(p0) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[FI1VREG:%[0-9]+]] = ADDri %fixed-stack.[[FI1]], 0, 14, _, _
- %3(s1) = G_LOAD %2(p0)
+ %3(s1) = G_LOAD %2(p0) :: (load 1)
; CHECK: {{%[0-9]+}} = LDRBi12 [[FI1VREG]], 0, 14, _
BX_RET 14, _
@@ -350,7 +350,7 @@ body: |
%0(p0) = COPY %r0
- %1(s32) = G_LOAD %0(p0)
+ %1(s32) = G_LOAD %0(p0) :: (load 4)
; CHECK: %[[V]] = VLDRS %[[P]], 0, 14, _
%s0 = COPY %1
@@ -377,7 +377,7 @@ body: |
%0(p0) = COPY %r0
- %1(s64) = G_LOAD %0(p0)
+ %1(s64) = G_LOAD %0(p0) :: (load 8)
; CHECK: %[[V]] = VLDRD %[[P]], 0, 14, _
%d0 = COPY %1
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir?rev=295476&r1=295475&r2=295476&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir Fri Feb 17 12:50:15 2017
@@ -157,9 +157,9 @@ body: |
; This is legal, so we should find it unchanged in the output
; CHECK: [[FIVREG:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[FRAME_INDEX]]
- ; CHECK: {{%[0-9]+}}(s32) = G_LOAD [[FIVREG]](p0)
+ ; CHECK: {{%[0-9]+}}(s32) = G_LOAD [[FIVREG]](p0) :: (load 4)
%0(p0) = G_FRAME_INDEX %fixed-stack.2
- %1(s32) = G_LOAD %0(p0)
+ %1(s32) = G_LOAD %0(p0) :: (load 4)
BX_RET 14, _
...
---
@@ -190,12 +190,12 @@ body: |
; CHECK-DAG: {{%[0-9]+}}(s1) = G_LOAD %0
; CHECK-DAG: {{%[0-9]+}}(p0) = G_LOAD %0
%0(p0) = COPY %r0
- %1(s32) = G_LOAD %0(p0)
- %2(s16) = G_LOAD %0(p0)
- %3(s8) = G_LOAD %0(p0)
- %4(s1) = G_LOAD %0(p0)
- %5(p0) = G_LOAD %0(p0)
- %6(s64) = G_LOAD %0(p0)
+ %1(s32) = G_LOAD %0(p0) :: (load 4)
+ %2(s16) = G_LOAD %0(p0) :: (load 2)
+ %3(s8) = G_LOAD %0(p0) :: (load 1)
+ %4(s1) = G_LOAD %0(p0) :: (load 1)
+ %5(p0) = G_LOAD %0(p0) :: (load 4)
+ %6(s64) = G_LOAD %0(p0) :: (load 8)
BX_RET 14, _
...
---
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=295476&r1=295475&r2=295476&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Fri Feb 17 12:50:15 2017
@@ -145,12 +145,12 @@ body: |
bb.0:
liveins: %r0
%0(p0) = COPY %r0
- %6(s64) = G_LOAD %0
- %1(s32) = G_LOAD %0
- %2(s16) = G_LOAD %0
- %3(s8) = G_LOAD %0
- %4(s1) = G_LOAD %0
- %5(p0) = G_LOAD %0
+ %6(s64) = G_LOAD %0 :: (load 8)
+ %1(s32) = G_LOAD %0 :: (load 4)
+ %2(s16) = G_LOAD %0 :: (load 2)
+ %3(s8) = G_LOAD %0 :: (load 1)
+ %4(s1) = G_LOAD %0 :: (load 1)
+ %5(p0) = G_LOAD %0 :: (load 8)
BX_RET 14, _, implicit %r0
...
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