[llvm] r295321 - [ARM] GlobalISel: Select floating point loads

[Diana Picus via llvm-commits]

I'll look into it, thanks!

On 16 February 2017 at 18:34, Ahmed Bougacha <ahmed.bougacha at gmail.com> wrote:
> On Thu, Feb 16, 2017 at 6:10 AM, Diana Picus via llvm-commits
> <llvm-commits at lists.llvm.org> wrote:
>> Author: rovka
>> Date: Thu Feb 16 08:10:50 2017
>> New Revision: 295321
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=295321&view=rev
>> Log:
>> [ARM] GlobalISel: Select floating point loads
>>
>> Modified:
>>     llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
>>     llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp?rev=295321&r1=295320&r2=295321&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp Thu Feb 16 08:10:50 2017
>> @@ -189,15 +189,27 @@ static unsigned selectSimpleExtOpc(unsig
>>
>>  /// Select the opcode for simple loads. For types smaller than 32 bits, the
>>  /// value will be zero extended.
>> -static unsigned selectLoadOpCode(unsigned Size) {
>> +static unsigned selectLoadOpCode(unsigned RegBank, unsigned Size) {
>> +  if (RegBank == ARM::GPRRegBankID) {
>> +    switch (Size) {
>> +    case 1:
>> +    case 8:
>> +      return ARM::LDRBi12;
>> +    case 16:
>> +      return ARM::LDRH;
>> +    case 32:
>> +      return ARM::LDRi12;
>> +    }
>> +
>> +    llvm_unreachable("Unsupported size");
>> +  }
>> +
>> +  assert(RegBank == ARM::FPRRegBankID && "Unsupported register bank");
>>    switch (Size) {
>> -  case 1:
>> -  case 8:
>> -    return ARM::LDRBi12;
>> -  case 16:
>> -    return ARM::LDRH;
>>    case 32:
>> -    return ARM::LDRi12;
>> +    return ARM::VLDRS;
>> +  case 64:
>> +    return ARM::VLDRD;
>>    }
>>
>>    llvm_unreachable("Unsupported size");
>> @@ -290,13 +302,22 @@ bool ARMInstructionSelector::select(Mach
>>      MIB.addImm(0).add(predOps(ARMCC::AL)).add(condCodeOp());
>>      break;
>>    case G_LOAD: {
>> -    LLT ValTy = MRI.getType(I.getOperand(0).getReg());
>> +    unsigned Reg = I.getOperand(0).getReg();
>> +    unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID();
>> +
>> +    LLT ValTy = MRI.getType(Reg);
>>      const auto ValSize = ValTy.getSizeInBits();
>>
>> -    if (ValSize != 32 && ValSize != 16 && ValSize != 8 && ValSize != 1)
>> +    if (ValSize != 64 && ValSize != 32 && ValSize != 16 && ValSize != 8 &&
>> +        ValSize != 1)
>>        return false;
>
> Minor detail: this might be easier to read (and avoids needing to
> update somewhat redundant information) if selectLoadOpCode returned an
> "invalid" opcode for things it doesn't support.
>
> -Ahmed
>
>> -    const auto NewOpc = selectLoadOpCode(ValSize);
>> +    assert((ValSize != 64 || RegBank == ARM::FPRRegBankID) &&
>> +           "64-bit values should live in the FPR");
>> +    assert((ValSize != 64 || TII.getSubtarget().hasVFP2()) &&
>> +           "Don't know how to load 64-bit value without VFP");
>> +
>> +    const auto NewOpc = selectLoadOpCode(RegBank, ValSize);
>>      I.setDesc(TII.get(NewOpc));
>>
>>      if (NewOpc == ARM::LDRH)
>>
>> Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=295321&r1=295320&r2=295321&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
>> +++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Thu Feb 16 08:10:50 2017
>> @@ -13,6 +13,8 @@
>>    define void @test_fadd_s64() #0 { ret void }
>>
>>    define void @test_load_from_stack() { ret void }
>> +  define void @test_load_f32() #0 { ret void }
>> +  define void @test_load_f64() #0 { ret void }
>>
>>    define void @test_soft_fp_double() #0 { ret void }
>>
>> @@ -331,6 +333,60 @@ body:             |
>>      ; CHECK: BX_RET 14, _
>>  ...
>>  ---
>> +name:            test_load_f32
>> +# CHECK-LABEL: name: test_load_f32
>> +legalized:       true
>> +regBankSelected: true
>> +selected:        false
>> +# CHECK: selected: true
>> +registers:
>> +  - { id: 0, class: gprb }
>> +  - { id: 1, class: fprb }
>> +# CHECK-DAG: id: [[P:[0-9]+]], class: gpr
>> +# CHECK-DAG: id: [[V:[0-9]+]], class: spr
>> +body:             |
>> +  bb.0:
>> +    liveins: %r0, %r1, %r2, %r3
>> +
>> +    %0(p0) = COPY %r0
>> +
>> +    %1(s32) = G_LOAD %0(p0)
>> +    ; CHECK: %[[V]] = VLDRS %[[P]], 0, 14, _
>> +
>> +    %s0 = COPY %1
>> +    ; CHECK: %s0 = COPY %[[V]]
>> +
>> +    BX_RET 14, _, implicit %s0
>> +    ; CHECK: BX_RET 14, _, implicit %s0
>> +...
>> +---
>> +name:            test_load_f64
>> +# CHECK-LABEL: name: test_load_f64
>> +legalized:       true
>> +regBankSelected: true
>> +selected:        false
>> +# CHECK: selected: true
>> +registers:
>> +  - { id: 0, class: gprb }
>> +  - { id: 1, class: fprb }
>> +# CHECK-DAG: id: [[P:[0-9]+]], class: gpr
>> +# CHECK-DAG: id: [[V:[0-9]+]], class: dpr
>> +body:             |
>> +  bb.0:
>> +    liveins: %r0, %r1, %r2, %r3
>> +
>> +    %0(p0) = COPY %r0
>> +
>> +    %1(s64) = G_LOAD %0(p0)
>> +    ; CHECK: %[[V]] = VLDRD %[[P]], 0, 14, _
>> +
>> +    %d0 = COPY %1
>> +    ; CHECK: %d0 = COPY %[[V]]
>> +
>> +    BX_RET 14, _, implicit %d0
>> +    ; CHECK: BX_RET 14, _, implicit %d0
>> +...
>> +---
>>  name:            test_soft_fp_double
>>  # CHECK-LABEL: name: test_soft_fp_double
>>  legalized:       true
>>
>>
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