[PATCH] D30081: [PPC] Eliminate more compare instructions using record-form operation

[Hiroshi Inoue via Phabricator via llvm-commits]

inouehrs created this revision.

PPC backend eliminates compare instructions by using record-form instructions in PPCInstrInfo::optimizeCompareInstr, which is called from peephole optimization pass.
This patch improves this optimization to eliminate more compare instructions in two types of common case.

comparison against a constant 1 or -1
-------------------------------------

The record-form instructions set CR bit based on signed comparison against 0. So, the current implementation does not exploit the record-form instruction for comparison against a non-zero constant.
This patch enables record-form optimization for constant of 1 or -1 if possible; it changes  the condition "greater than -1" into "greater than or equal to 0" and "less than 1" into "less than or equal to 0".
With this patch, compare can be eliminated in the following code sequence, as an example.

  uint64_t a, b;
  if ((a | b) & 0x8000000000000000ull) { ... }
  else { ... }



`andi` for 32-bit comparison on PPC64
-------------------------------------

Since record-form instructions execute 64-bit signed comparison and so we have limitation in eliminating 32-bit comparison, i.e. with cmplwi, using the record-form. The original implementation already has such checks but `andi.` is not recognized as an instruction which executes implicit zero extension and hence safe to convert into record-form if used for equality check.

  %1 = and i32 %a, 10
  %2 = icmp ne i32 %1, 0
  br i1 %2, label %foo, label %bar

In this simple example, LLVM generates andi. + cmplwi + beq on PPC64.
This patch make it possible to eliminate the cmplwi for this case.
I added `andi.`, `andis.`, and `rlwinm` variants such as `rotrwi`for optimization targets if it is safe to do so.


https://reviews.llvm.org/D30081

Files:
  lib/Target/PowerPC/PPCInstrInfo.cpp
  test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll

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