[llvm] r295346 - [x86] add more tests of select of constants; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 16 10:15:16 PST 2017
Author: spatel
Date: Thu Feb 16 12:15:16 2017
New Revision: 295346
URL: http://llvm.org/viewvc/llvm-project?rev=295346&view=rev
Log:
[x86] add more tests of select of constants; NFC
Modified:
llvm/trunk/test/CodeGen/X86/select_const.ll
Modified: llvm/trunk/test/CodeGen/X86/select_const.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/select_const.ll?rev=295346&r1=295345&r2=295346&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/select_const.ll (original)
+++ llvm/trunk/test/CodeGen/X86/select_const.ll Thu Feb 16 12:15:16 2017
@@ -1,6 +1,11 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+; Select of constants: control flow / conditional moves can always be replaced by logic+math (but may not be worth it?).
+; Test the zeroext/signext variants of each pattern to see if that makes a difference.
+
+; select Cond, 0, 1 --> zext (!Cond)
+
define i32 @select_0_or_1(i1 %cond) {
; CHECK-LABEL: select_0_or_1:
; CHECK: # BB#0:
@@ -8,7 +13,6 @@ define i32 @select_0_or_1(i1 %cond) {
; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: retq
-;
%sel = select i1 %cond, i32 0, i32 1
ret i32 %sel
}
@@ -19,18 +23,29 @@ define i32 @select_0_or_1_zeroext(i1 zer
; CHECK-NEXT: xorb $1, %dil
; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: retq
-;
%sel = select i1 %cond, i32 0, i32 1
ret i32 %sel
}
+define i32 @select_0_or_1_signext(i1 signext %cond) {
+; CHECK-LABEL: select_0_or_1_signext:
+; CHECK: # BB#0:
+; CHECK-NEXT: notb %dil
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: andl $1, %eax
+; CHECK-NEXT: retq
+ %sel = select i1 %cond, i32 0, i32 1
+ ret i32 %sel
+}
+
+; select Cond, 1, 0 --> zext (Cond)
+
define i32 @select_1_or_0(i1 %cond) {
; CHECK-LABEL: select_1_or_0:
; CHECK: # BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
-;
%sel = select i1 %cond, i32 1, i32 0
ret i32 %sel
}
@@ -40,11 +55,22 @@ define i32 @select_1_or_0_zeroext(i1 zer
; CHECK: # BB#0:
; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: retq
-;
%sel = select i1 %cond, i32 1, i32 0
ret i32 %sel
}
+define i32 @select_1_or_0_signext(i1 signext %cond) {
+; CHECK-LABEL: select_1_or_0_signext:
+; CHECK: # BB#0:
+; CHECK-NEXT: andb $1, %dil
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: retq
+ %sel = select i1 %cond, i32 1, i32 0
+ ret i32 %sel
+}
+
+; select Cond, 0, -1 --> sext (!Cond)
+
define i32 @select_0_or_neg1(i1 %cond) {
; CHECK-LABEL: select_0_or_neg1:
; CHECK: # BB#0:
@@ -52,7 +78,6 @@ define i32 @select_0_or_neg1(i1 %cond) {
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: leal -1(%rdi), %eax
; CHECK-NEXT: retq
-;
%sel = select i1 %cond, i32 0, i32 -1
ret i32 %sel
}
@@ -63,11 +88,23 @@ define i32 @select_0_or_neg1_zeroext(i1
; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: decl %eax
; CHECK-NEXT: retq
-;
%sel = select i1 %cond, i32 0, i32 -1
ret i32 %sel
}
+define i32 @select_0_or_neg1_signext(i1 signext %cond) {
+; CHECK-LABEL: select_0_or_neg1_signext:
+; CHECK: # BB#0:
+; CHECK-NEXT: andb $1, %dil
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: decl %eax
+; CHECK-NEXT: retq
+ %sel = select i1 %cond, i32 0, i32 -1
+ ret i32 %sel
+}
+
+; select Cond, -1, 0 --> sext (Cond)
+
define i32 @select_neg1_or_0(i1 %cond) {
; CHECK-LABEL: select_neg1_or_0:
; CHECK: # BB#0:
@@ -76,7 +113,6 @@ define i32 @select_neg1_or_0(i1 %cond) {
; CHECK-NEXT: movl $-1, %eax
; CHECK-NEXT: cmovel %ecx, %eax
; CHECK-NEXT: retq
-;
%sel = select i1 %cond, i32 -1, i32 0
ret i32 %sel
}
@@ -89,11 +125,134 @@ define i32 @select_neg1_or_0_zeroext(i1
; CHECK-NEXT: movl $-1, %eax
; CHECK-NEXT: cmovel %ecx, %eax
; CHECK-NEXT: retq
-;
%sel = select i1 %cond, i32 -1, i32 0
ret i32 %sel
}
+define i32 @select_neg1_or_0_signext(i1 signext %cond) {
+; CHECK-LABEL: select_neg1_or_0_signext:
+; CHECK: # BB#0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: testb $1, %dil
+; CHECK-NEXT: movl $-1, %eax
+; CHECK-NEXT: cmovel %ecx, %eax
+; CHECK-NEXT: retq
+ %sel = select i1 %cond, i32 -1, i32 0
+ ret i32 %sel
+}
+
+; select Cond, C+1, C --> add (zext Cond), C
+
+define i32 @select_Cplus1_C(i1 %cond) {
+; CHECK-LABEL: select_Cplus1_C:
+; CHECK: # BB#0:
+; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: andl $1, %edi
+; CHECK-NEXT: leal 41(%rdi), %eax
+; CHECK-NEXT: retq
+ %sel = select i1 %cond, i32 42, i32 41
+ ret i32 %sel
+}
+
+define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) {
+; CHECK-LABEL: select_Cplus1_C_zeroext:
+; CHECK: # BB#0:
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: addl $41, %eax
+; CHECK-NEXT: retq
+ %sel = select i1 %cond, i32 42, i32 41
+ ret i32 %sel
+}
+
+define i32 @select_Cplus1_C_signext(i1 signext %cond) {
+; CHECK-LABEL: select_Cplus1_C_signext:
+; CHECK: # BB#0:
+; CHECK-NEXT: andb $1, %dil
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: addl $41, %eax
+; CHECK-NEXT: retq
+ %sel = select i1 %cond, i32 42, i32 41
+ ret i32 %sel
+}
+
+; select Cond, C, C+1 --> add (sext Cond), C
+
+define i32 @select_C_Cplus1(i1 %cond) {
+; CHECK-LABEL: select_C_Cplus1:
+; CHECK: # BB#0:
+; CHECK-NEXT: andb $1, %dil
+; CHECK-NEXT: cmpb $1, %dil
+; CHECK-NEXT: movl $41, %eax
+; CHECK-NEXT: adcl $0, %eax
+; CHECK-NEXT: retq
+ %sel = select i1 %cond, i32 41, i32 42
+ ret i32 %sel
+}
+
+define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) {
+; CHECK-LABEL: select_C_Cplus1_zeroext:
+; CHECK: # BB#0:
+; CHECK-NEXT: cmpb $1, %dil
+; CHECK-NEXT: movl $41, %eax
+; CHECK-NEXT: adcl $0, %eax
+; CHECK-NEXT: retq
+ %sel = select i1 %cond, i32 41, i32 42
+ ret i32 %sel
+}
+
+define i32 @select_C_Cplus1_signext(i1 signext %cond) {
+; CHECK-LABEL: select_C_Cplus1_signext:
+; CHECK: # BB#0:
+; CHECK-NEXT: andb $1, %dil
+; CHECK-NEXT: cmpb $1, %dil
+; CHECK-NEXT: movl $41, %eax
+; CHECK-NEXT: adcl $0, %eax
+; CHECK-NEXT: retq
+ %sel = select i1 %cond, i32 41, i32 42
+ ret i32 %sel
+}
+
+; In general, select of 2 constants could be:
+; select Cond, C1, C2 --> add (mul (zext Cond), C1-C2), C2 --> add (and (sext Cond), C1-C2), C2
+
+define i32 @select_C1_C2(i1 %cond) {
+; CHECK-LABEL: select_C1_C2:
+; CHECK: # BB#0:
+; CHECK-NEXT: testb $1, %dil
+; CHECK-NEXT: movl $421, %ecx # imm = 0x1A5
+; CHECK-NEXT: movl $42, %eax
+; CHECK-NEXT: cmovnel %ecx, %eax
+; CHECK-NEXT: retq
+ %sel = select i1 %cond, i32 421, i32 42
+ ret i32 %sel
+}
+
+define i32 @select_C1_C2_zeroext(i1 zeroext %cond) {
+; CHECK-LABEL: select_C1_C2_zeroext:
+; CHECK: # BB#0:
+; CHECK-NEXT: testb %dil, %dil
+; CHECK-NEXT: movl $421, %ecx # imm = 0x1A5
+; CHECK-NEXT: movl $42, %eax
+; CHECK-NEXT: cmovnel %ecx, %eax
+; CHECK-NEXT: retq
+ %sel = select i1 %cond, i32 421, i32 42
+ ret i32 %sel
+}
+
+define i32 @select_C1_C2_signext(i1 signext %cond) {
+; CHECK-LABEL: select_C1_C2_signext:
+; CHECK: # BB#0:
+; CHECK-NEXT: testb $1, %dil
+; CHECK-NEXT: movl $421, %ecx # imm = 0x1A5
+; CHECK-NEXT: movl $42, %eax
+; CHECK-NEXT: cmovnel %ecx, %eax
+; CHECK-NEXT: retq
+ %sel = select i1 %cond, i32 421, i32 42
+ ret i32 %sel
+}
+
+; select (x == 2), 2, (x + 1) --> select (x == 2), x, (x + 1)
+
define i64 @select_2_or_inc(i64 %x) {
; CHECK-LABEL: select_2_or_inc:
; CHECK: # BB#0:
@@ -101,7 +260,6 @@ define i64 @select_2_or_inc(i64 %x) {
; CHECK-NEXT: cmpq $2, %rdi
; CHECK-NEXT: cmoveq %rdi, %rax
; CHECK-NEXT: retq
-;
%cmp = icmp eq i64 %x, 2
%add = add i64 %x, 1
%retval.0 = select i1 %cmp, i64 2, i64 %add
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