[PATCH] D29953: [ARM] Classification Improvements to ARM Sched-Models. NFCI.

[Diana Picus via Phabricator via llvm-commits]

rovka added a comment.

Could you also add tests for some of the other instructions, like t2SDIV, t2LDR etc? Or are they already covered elsewhere?



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Comment at: lib/Target/ARM/ARMInstrThumb2.td:983
+                   [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]>,
+            Sched<[WriteLd]> {
     bits<4> Rt;
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Instructions defined with this can get either the IIC_iLoad_i or the IIC_iLoad_bh_i itinerary, and they seem to be slightly different (at least for A9). Does this matter in practice?


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Comment at: lib/Target/ARM/ARMInstrThumb2.td:1069
 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
 multiclass T2I_st<bits<2> opcod, string opc,
                   InstrItinClass iii, InstrItinClass iis, RegisterClass target,
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Same as above.


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Comment at: lib/Target/ARM/ARMScheduleR52.td:170
 def : SchedAlias<WriteMAC64Hi, R52WriteMACHi>;
+def : SchedAlias<WriteST, R52WriteST>;
 
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Shouldn't you also define an alias between WriteLd and R52WriteLd?


https://reviews.llvm.org/D29953