[PATCH] D28655: [NDS32 18/46] Add 32-bit Load/Store instructions with [Reg + Reg << Imm] addressing mode

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 updated this revision to Diff 88689.
shiva0217 retitled this revision from "[NDS32 18/22] add NDS32 Assembly Parser" to "[NDS32 18/46] Add 32-bit Load/Store instructions with [Reg + Reg << Imm] addressing mode".
shiva0217 edited the summary of this revision.

https://reviews.llvm.org/D28655

Files:
  lib/Target/NDS32/InstPrinter/NDS32InstPrinter.cpp
  lib/Target/NDS32/InstPrinter/NDS32InstPrinter.h
  lib/Target/NDS32/NDS32ISelDAGToDAG.cpp
  lib/Target/NDS32/NDS32InstrFormats.td
  lib/Target/NDS32/NDS32InstrInfo.td
  lib/Target/NDS32/NDS32Predicate.td
  test/CodeGen/NDS32/load-store-insns.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D28655.88689.patch
Type: text/x-patch
Size: 10815 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170216/2fbd3b04/attachment.bin>