[PATCH] D29959: x86 interrupt calling convention: only save xmm registers if the target supports SSE

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb added a comment.

I only have a minor comment about the test.

Given how simple is function @test_isr_sse_clobbers, I wouldn't be surprised if the codegen with/without -O0 is the same.
If so, then you should be able to get rid of CHECK0; at the moment, CHECK and CHECK0 are basically equivalent classes of checks.

I also suggest to automatically generate CHECK lines using 'update_llc_test_checks.py' (it is up to you).
Since the body of @test_isr_sse_clobbers is very small, I don't expect to see many automatically generated CHECK lines anyway.


https://reviews.llvm.org/D29959