[PATCH] D29935: [RISCV 13/n] Codegen for conditional branches

[Alex Bradbury via Phabricator via llvm-commits]

asb created this revision.

A good portion of this patch is the extra functions that needed to be implemented to support the test case. e.g. storeRegToStackSlot, loadRegFromStackSlot, eliminateFrameIndex.

Setting `ISD::BR_CC` to Expand may appear non-obvious on an architecture with branch+cmp instructions. However, I found it much easier to deal with matching the expanded form.

I had to change `simm13_lsb0` and `simm21_lsb0` to use the `Operand<OtherVT>` class rather than `Operand<i32>` in order to keep tablegen happy. This isn't a big deal, but it does seem a shame to lose the uniformity across immediate types when there's not an obvious benefit (I'm hoping a tablegen expert will educate me on what I'm missing here!).


https://reviews.llvm.org/D29935

Files:
  lib/Target/RISCV/RISCV.h
  lib/Target/RISCV/RISCVCallingConv.td
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVInstrInfo.cpp
  lib/Target/RISCV/RISCVInstrInfo.h
  lib/Target/RISCV/RISCVInstrInfo.td
  lib/Target/RISCV/RISCVRegisterInfo.cpp
  lib/Target/RISCV/RISCVRegisterInfo.h
  test/CodeGen/RISCV/branch.ll

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