[PATCH] D29933: [RISCV 11/n] Initial codegen support for ALU operations

[Alex Bradbury via Phabricator via llvm-commits]

asb created this revision.
Herald added a subscriber: mgorny.

I think this is a fair approximation of the minimum necessary for some sort of testable codegen - though if people have any ideas on splitting things up further I'm all ears. Frame handling, and proper function prologue/epilogue handling is left for a later patch.

For the time being, this primarily targets RV32. Last I heard, @kparzysz is still hoping to get time to finish some prototype patches for his RFC on variable-sized register classes <http://lists.llvm.org/pipermail/llvm-dev/2016-September/105027.html>. In the ideal case, the RISCV backend will build upon these patches and act as a demonstrator to prove the approach. However, if it looks like that isn't going to happen any time soon then I'll bite the bullet and add in all the necessary 64-bit code paths and duplicated instruction definitions.


https://reviews.llvm.org/D29933

Files:
  lib/Target/RISCV/CMakeLists.txt
  lib/Target/RISCV/LLVMBuild.txt
  lib/Target/RISCV/RISCV.h
  lib/Target/RISCV/RISCV.td
  lib/Target/RISCV/RISCVAsmPrinter.cpp
  lib/Target/RISCV/RISCVCallingConv.td
  lib/Target/RISCV/RISCVFrameLowering.cpp
  lib/Target/RISCV/RISCVFrameLowering.h
  lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/RISCV/RISCVInstrInfo.cpp
  lib/Target/RISCV/RISCVInstrInfo.h
  lib/Target/RISCV/RISCVInstrInfo.td
  lib/Target/RISCV/RISCVMCInstLower.cpp
  lib/Target/RISCV/RISCVRegisterInfo.cpp
  lib/Target/RISCV/RISCVRegisterInfo.h
  lib/Target/RISCV/RISCVRegisterInfo.td
  lib/Target/RISCV/RISCVSubtarget.cpp
  lib/Target/RISCV/RISCVSubtarget.h
  lib/Target/RISCV/RISCVTargetMachine.cpp
  lib/Target/RISCV/RISCVTargetMachine.h
  test/CodeGen/RISCV/alu.ll
  test/CodeGen/RISCV/lit.local.cfg

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