[PATCH] D23567: [RISCV 9/10] Add support for disassembly

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 88332.
asb added a comment.

The previous version of this patch made the mistake when decoding a GPR of assuming you can use the parsed RegNo as an index into the register class. In the general case, a register class will have the registers in preferred allocation order, meaning this will fail. Instead, we have a GPRDecoderTable to select the appropriate register based on the parsed RegNo.


https://reviews.llvm.org/D23567

Files:
  lib/Target/RISCV/CMakeLists.txt
  lib/Target/RISCV/Disassembler/CMakeLists.txt
  lib/Target/RISCV/Disassembler/LLVMBuild.txt
  lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  lib/Target/RISCV/LLVMBuild.txt
  lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
  lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
  lib/Target/RISCV/RISCVInstrFormats.td
  lib/Target/RISCV/RISCVInstrInfo.td
  test/MC/RISCV/rv32i-valid.s

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