[PATCH] D29720: [X86][SSE] Attempt to break register dependencies during lowerBuildVector

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
Herald added a subscriber: igorb.

LowerBuildVectorv16i8/LowerBuildVectorv8i16 insert values into a UNDEF vector if the build vector doesn't contain any zero elements, resulting in register dependencies with a previous use of the register.

This patch attempts to break the register dependency by either always zeroing the vector before hand or (if we're inserting to the 0'th element) by using VZEXT_MOVL(SCALAR_TO_VECTOR(i32 AEXT(Elt))) which lowers to (V)MOVD and performs a similar function. Additionally (V)MOVD is a shorter instruction than PINSRB/PINSRW. We already do something similar for SSE41 PINSRD.

On pre-SSE41 LowerBuildVectorv16i8 we go a little further and use VZEXT_MOVL(SCALAR_TO_VECTOR(i32 ZEXT(Elt))) if the build vector contains zeros to avoid the vector zeroing at the cost of a scalar zero extension, which can probably be brought over to the other cases in a future patch in some cases (load folding etc.)


Repository:
  rL LLVM

https://reviews.llvm.org/D29720

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/avx512-intrinsics.ll
  test/CodeGen/X86/avx512bwvl-intrinsics.ll
  test/CodeGen/X86/avx512vl-intrinsics.ll
  test/CodeGen/X86/buildvec-insertvec.ll
  test/CodeGen/X86/promote-vec3.ll
  test/CodeGen/X86/shuffle-vs-trunc-512.ll
  test/CodeGen/X86/vec_cast2.ll
  test/CodeGen/X86/vector-shuffle-128-v16.ll
  test/CodeGen/X86/widen_bitops-0.ll
  test/CodeGen/X86/widen_conv-3.ll
  test/CodeGen/X86/widen_conv-4.ll

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