[llvm] r294472 - [Hexagon] Fix decoding conflict between A2_zxtb and A4_ext

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Feb  8 10:31:00 2017
New Revision: 294472

URL: http://llvm.org/viewvc/llvm-project?rev=294472&view=rev
Log:
[Hexagon] Fix decoding conflict between A2_zxtb and A4_ext

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td?rev=294472&r1=294471&r2=294472&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td Wed Feb  8 10:31:00 2017
@@ -436,6 +436,8 @@ def : InstAlias<"$Pd=cmp.ltu($Rs, $Rt)",
 // Rd=neg(Rs) is aliased to Rd=sub(#0,Rs)
 def : InstAlias<"$Rd = neg($Rs)",
       (A2_subri IntRegs:$Rd, 0, IntRegs:$Rs), 0>;
+def : InstAlias<"$Rd=zxtb($Rs)",
+      (A2_andir IntRegs:$Rd, IntRegs:$Rs, 255)>;
 
 def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>;
 def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=294472&r1=294471&r2=294472&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Wed Feb  8 10:31:00 2017
@@ -706,7 +706,7 @@ defm zxth : ALU32_2op_base<"zxth", 0b110
 // handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
 // immediate operand is set to '255'.
 
-let hasNewValue = 1, opNewValue = 0 in
+let hasNewValue = 1, opNewValue = 0, isPseudo = 1, isCodeGenOnly = 1 in
 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
   "$Rd=zxtb($Rs)", [] >;