[PATCH] D29528: [DAGCombiner] Push truncate through adde when the carry isn't used.

[Amaury SECHET via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL294394: [DAGCombiner] Push truncate through adde when the carry isn't used. (authored by deadalnix).

Changed prior to commit:
  https://reviews.llvm.org/D29528?vs=87289&id=87564#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D29528

Files:
  llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/trunk/test/CodeGen/X86/adde-carry.ll
  llvm/trunk/test/CodeGen/X86/known-bits.ll


Index: llvm/trunk/test/CodeGen/X86/known-bits.ll
===================================================================
--- llvm/trunk/test/CodeGen/X86/known-bits.ll
+++ llvm/trunk/test/CodeGen/X86/known-bits.ll
@@ -151,8 +151,7 @@
 ; X64-NEXT:    andq $-1024, %rdi # imm = 0xFC00
 ; X64-NEXT:    andq $-1024, %rsi # imm = 0xFC00
 ; X64-NEXT:    addq %rdi, %rsi
-; X64-NEXT:    sbbq %rax, %rax
-; X64-NEXT:    subl %eax, %edx
+; X64-NEXT:    adcl $0, %edx
 ; X64-NEXT:    shldq $54, %rsi, %rdx
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    retq
Index: llvm/trunk/test/CodeGen/X86/adde-carry.ll
===================================================================
--- llvm/trunk/test/CodeGen/X86/adde-carry.ll
+++ llvm/trunk/test/CodeGen/X86/adde-carry.ll
@@ -28,8 +28,7 @@
 ; CHECK-LABEL: b:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addq %rdx, %rsi
-; CHECK-NEXT:    sbbq %rax, %rax
-; CHECK-NEXT:    subl %eax, %ecx
+; CHECK-NEXT:    adcl $0, %ecx
 ; CHECK-NEXT:    movl %ecx, (%rdi)
 ; CHECK-NEXT:    retq
 entry:
@@ -48,8 +47,7 @@
 ; CHECK-LABEL: c:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addq %rdx, %rsi
-; CHECK-NEXT:    sbbq %rax, %rax
-; CHECK-NEXT:    subl %eax, %ecx
+; CHECK-NEXT:    adcl $0, %ecx
 ; CHECK-NEXT:    movw %cx, (%rdi)
 ; CHECK-NEXT:    retq
 entry:
@@ -68,8 +66,7 @@
 ; CHECK-LABEL: d:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addq %rdx, %rsi
-; CHECK-NEXT:    sbbq %rax, %rax
-; CHECK-NEXT:    subl %eax, %ecx
+; CHECK-NEXT:    adcl $0, %ecx
 ; CHECK-NEXT:    movb %cl, (%rdi)
 ; CHECK-NEXT:    retq
 entry:
@@ -165,8 +162,8 @@
 ; CHECK-NEXT:    adcq $0, %rdx
 ; CHECK-NEXT:    movq %rax, (%rdi)
 ; CHECK-NEXT:    addq 8(%rdi), %rdx
-; CHECK-NEXT:    sbbq %rax, %rax
 ; CHECK-NEXT:    movq %rdx, 8(%rdi)
+; CHECK-NEXT:    sbbl %eax, %eax
 ; CHECK-NEXT:    subl %eax, 16(%rdi)
 ; CHECK-NEXT:    retq
 entry:
Index: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7866,6 +7866,18 @@
       SimplifyDemandedBits(SDValue(N, 0)))
     return SDValue(N, 0);
 
+  // (trunc adde(X, Y, Carry)) -> (adde trunc(X), trunc(Y), Carry)
+  // When the adde's carry is not used.
+  if (N0.getOpcode() == ISD::ADDE && N0.hasOneUse() &&
+      !N0.getNode()->hasAnyUseOfValue(1) &&
+      (!LegalOperations || TLI.isOperationLegal(ISD::ADDE, VT))) {
+    SDLoc SL(N);
+    auto X = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(0));
+    auto Y = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
+    return DAG.getNode(ISD::ADDE, SL, DAG.getVTList(VT, MVT::Glue),
+                       X, Y, N0.getOperand(2));
+  }
+
   return SDValue();
 }
 


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