[llvm] r294394 - [DAGCombiner] Push truncate through adde when the carry isn't used.
Amaury Sechet via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 7 16:32:37 PST 2017
Author: deadalnix
Date: Tue Feb 7 18:32:36 2017
New Revision: 294394
URL: http://llvm.org/viewvc/llvm-project?rev=294394&view=rev
Log:
[DAGCombiner] Push truncate through adde when the carry isn't used.
Summary: As per title.
Reviewers: mkuper, spatel, bkramer, RKSimon, zvi
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D29528
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/X86/adde-carry.ll
llvm/trunk/test/CodeGen/X86/known-bits.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=294394&r1=294393&r2=294394&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Feb 7 18:32:36 2017
@@ -7866,6 +7866,18 @@ SDValue DAGCombiner::visitTRUNCATE(SDNod
SimplifyDemandedBits(SDValue(N, 0)))
return SDValue(N, 0);
+ // (trunc adde(X, Y, Carry)) -> (adde trunc(X), trunc(Y), Carry)
+ // When the adde's carry is not used.
+ if (N0.getOpcode() == ISD::ADDE && N0.hasOneUse() &&
+ !N0.getNode()->hasAnyUseOfValue(1) &&
+ (!LegalOperations || TLI.isOperationLegal(ISD::ADDE, VT))) {
+ SDLoc SL(N);
+ auto X = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(0));
+ auto Y = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
+ return DAG.getNode(ISD::ADDE, SL, DAG.getVTList(VT, MVT::Glue),
+ X, Y, N0.getOperand(2));
+ }
+
return SDValue();
}
Modified: llvm/trunk/test/CodeGen/X86/adde-carry.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/adde-carry.ll?rev=294394&r1=294393&r2=294394&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/adde-carry.ll (original)
+++ llvm/trunk/test/CodeGen/X86/adde-carry.ll Tue Feb 7 18:32:36 2017
@@ -28,8 +28,7 @@ define void @b(i32* nocapture %r, i64 %a
; CHECK-LABEL: b:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addq %rdx, %rsi
-; CHECK-NEXT: sbbq %rax, %rax
-; CHECK-NEXT: subl %eax, %ecx
+; CHECK-NEXT: adcl $0, %ecx
; CHECK-NEXT: movl %ecx, (%rdi)
; CHECK-NEXT: retq
entry:
@@ -48,8 +47,7 @@ define void @c(i16* nocapture %r, i64 %a
; CHECK-LABEL: c:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addq %rdx, %rsi
-; CHECK-NEXT: sbbq %rax, %rax
-; CHECK-NEXT: subl %eax, %ecx
+; CHECK-NEXT: adcl $0, %ecx
; CHECK-NEXT: movw %cx, (%rdi)
; CHECK-NEXT: retq
entry:
@@ -68,8 +66,7 @@ define void @d(i8* nocapture %r, i64 %a,
; CHECK-LABEL: d:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addq %rdx, %rsi
-; CHECK-NEXT: sbbq %rax, %rax
-; CHECK-NEXT: subl %eax, %ecx
+; CHECK-NEXT: adcl $0, %ecx
; CHECK-NEXT: movb %cl, (%rdi)
; CHECK-NEXT: retq
entry:
@@ -165,8 +162,8 @@ define void @muladd(%accumulator* nocapt
; CHECK-NEXT: adcq $0, %rdx
; CHECK-NEXT: movq %rax, (%rdi)
; CHECK-NEXT: addq 8(%rdi), %rdx
-; CHECK-NEXT: sbbq %rax, %rax
; CHECK-NEXT: movq %rdx, 8(%rdi)
+; CHECK-NEXT: sbbl %eax, %eax
; CHECK-NEXT: subl %eax, 16(%rdi)
; CHECK-NEXT: retq
entry:
Modified: llvm/trunk/test/CodeGen/X86/known-bits.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/known-bits.ll?rev=294394&r1=294393&r2=294394&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/known-bits.ll (original)
+++ llvm/trunk/test/CodeGen/X86/known-bits.ll Tue Feb 7 18:32:36 2017
@@ -151,8 +151,7 @@ define i128 @knownbits_mask_addc_shl(i64
; X64-NEXT: andq $-1024, %rdi # imm = 0xFC00
; X64-NEXT: andq $-1024, %rsi # imm = 0xFC00
; X64-NEXT: addq %rdi, %rsi
-; X64-NEXT: sbbq %rax, %rax
-; X64-NEXT: subl %eax, %edx
+; X64-NEXT: adcl $0, %edx
; X64-NEXT: shldq $54, %rsi, %rdx
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: retq
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