[llvm] r294365 - [X86][SSE] Add SSE2 build vector insertion tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 7 14:23:12 PST 2017
Author: rksimon
Date: Tue Feb 7 16:23:12 2017
New Revision: 294365
URL: http://llvm.org/viewvc/llvm-project?rev=294365&view=rev
Log:
[X86][SSE] Add SSE2 build vector insertion tests
Modified:
llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll
Modified: llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll?rev=294365&r1=294364&r2=294365&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll (original)
+++ llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll Tue Feb 7 16:23:12 2017
@@ -1,15 +1,29 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE41
define void @foo(<3 x float> %in, <4 x i8>* nocapture %out) nounwind {
-; CHECK-LABEL: foo:
-; CHECK: # BB#0:
-; CHECK-NEXT: cvttps2dq %xmm0, %xmm0
-; CHECK-NEXT: movl $255, %eax
-; CHECK-NEXT: pinsrd $3, %eax, %xmm0
-; CHECK-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
-; CHECK-NEXT: movd %xmm0, (%rdi)
-; CHECK-NEXT: retq
+; SSE2-LABEL: foo:
+; SSE2: # BB#0:
+; SSE2-NEXT: cvttps2dq %xmm0, %xmm0
+; SSE2-NEXT: movl $255, %eax
+; SSE2-NEXT: movd %eax, %xmm1
+; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
+; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
+; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT: packuswb %xmm0, %xmm0
+; SSE2-NEXT: packuswb %xmm0, %xmm0
+; SSE2-NEXT: movd %xmm0, (%rdi)
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: foo:
+; SSE41: # BB#0:
+; SSE41-NEXT: cvttps2dq %xmm0, %xmm0
+; SSE41-NEXT: movl $255, %eax
+; SSE41-NEXT: pinsrd $3, %eax, %xmm0
+; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
+; SSE41-NEXT: movd %xmm0, (%rdi)
+; SSE41-NEXT: retq
%t0 = fptoui <3 x float> %in to <3 x i8>
%t1 = shufflevector <3 x i8> %t0, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
%t2 = insertelement <4 x i8> %t1, i8 -1, i32 3
@@ -21,10 +35,21 @@ define void @foo(<3 x float> %in, <4 x i
; blend with a zero vector if the build_vector contains negative zero.
define <4 x float> @test_negative_zero_1(<4 x float> %A) {
-; CHECK-LABEL: test_negative_zero_1:
-; CHECK: # BB#0: # %entry
-; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2],zero
-; CHECK-NEXT: retq
+; SSE2-LABEL: test_negative_zero_1:
+; SSE2: # BB#0: # %entry
+; SSE2-NEXT: movaps %xmm0, %xmm1
+; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
+; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-NEXT: xorps %xmm2, %xmm2
+; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
+; SSE2-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: test_negative_zero_1:
+; SSE41: # BB#0: # %entry
+; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2],zero
+; SSE41-NEXT: retq
entry:
%0 = extractelement <4 x float> %A, i32 0
%1 = insertelement <4 x float> undef, float %0, i32 0
@@ -48,12 +73,19 @@ entry:
}
define <4 x float> @test_buildvector_v4f32_register(float %f0, float %f1, float %f2, float %f3) {
-; CHECK-LABEL: test_buildvector_v4f32_register:
-; CHECK: # BB#0:
-; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
-; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
-; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
-; CHECK-NEXT: retq
+; SSE2-LABEL: test_buildvector_v4f32_register:
+; SSE2: # BB#0:
+; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
+; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: test_buildvector_v4f32_register:
+; SSE41: # BB#0:
+; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
+; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
+; SSE41-NEXT: retq
%ins0 = insertelement <4 x float> undef, float %f0, i32 0
%ins1 = insertelement <4 x float> %ins0, float %f1, i32 1
%ins2 = insertelement <4 x float> %ins1, float %f2, i32 2
@@ -62,13 +94,24 @@ define <4 x float> @test_buildvector_v4f
}
define <4 x float> @test_buildvector_v4f32_load(float* %p0, float* %p1, float* %p2, float* %p3) {
-; CHECK-LABEL: test_buildvector_v4f32_load:
-; CHECK: # BB#0:
-; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
-; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
-; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
-; CHECK-NEXT: retq
+; SSE2-LABEL: test_buildvector_v4f32_load:
+; SSE2: # BB#0:
+; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: test_buildvector_v4f32_load:
+; SSE41: # BB#0:
+; SSE41-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
+; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
+; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
+; SSE41-NEXT: retq
%f0 = load float, float* %p0, align 4
%f1 = load float, float* %p1, align 4
%f2 = load float, float* %p2, align 4
@@ -81,12 +124,20 @@ define <4 x float> @test_buildvector_v4f
}
define <4 x float> @test_buildvector_v4f32_partial_load(float %f0, float %f1, float %f2, float* %p3) {
-; CHECK-LABEL: test_buildvector_v4f32_partial_load:
-; CHECK: # BB#0:
-; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
-; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
-; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
-; CHECK-NEXT: retq
+; SSE2-LABEL: test_buildvector_v4f32_partial_load:
+; SSE2: # BB#0:
+; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
+; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: test_buildvector_v4f32_partial_load:
+; SSE41: # BB#0:
+; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
+; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
+; SSE41-NEXT: retq
%f3 = load float, float* %p3, align 4
%ins0 = insertelement <4 x float> undef, float %f0, i32 0
%ins1 = insertelement <4 x float> %ins0, float %f1, i32 1
@@ -96,13 +147,24 @@ define <4 x float> @test_buildvector_v4f
}
define <4 x i32> @test_buildvector_v4i32_register(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
-; CHECK-LABEL: test_buildvector_v4i32_register:
-; CHECK: # BB#0:
-; CHECK-NEXT: movd %edi, %xmm0
-; CHECK-NEXT: pinsrd $1, %esi, %xmm0
-; CHECK-NEXT: pinsrd $2, %edx, %xmm0
-; CHECK-NEXT: pinsrd $3, %ecx, %xmm0
-; CHECK-NEXT: retq
+; SSE2-LABEL: test_buildvector_v4i32_register:
+; SSE2: # BB#0:
+; SSE2-NEXT: movd %ecx, %xmm0
+; SSE2-NEXT: movd %esi, %xmm1
+; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE2-NEXT: movd %edx, %xmm2
+; SSE2-NEXT: movd %edi, %xmm0
+; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: test_buildvector_v4i32_register:
+; SSE41: # BB#0:
+; SSE41-NEXT: movd %edi, %xmm0
+; SSE41-NEXT: pinsrd $1, %esi, %xmm0
+; SSE41-NEXT: pinsrd $2, %edx, %xmm0
+; SSE41-NEXT: pinsrd $3, %ecx, %xmm0
+; SSE41-NEXT: retq
%ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0
%ins1 = insertelement <4 x i32> %ins0, i32 %a1, i32 1
%ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2
@@ -111,11 +173,19 @@ define <4 x i32> @test_buildvector_v4i32
}
define <4 x i32> @test_buildvector_v4i32_partial(i32 %a0, i32 %a3) {
-; CHECK-LABEL: test_buildvector_v4i32_partial:
-; CHECK: # BB#0:
-; CHECK-NEXT: movd %edi, %xmm0
-; CHECK-NEXT: pinsrd $3, %esi, %xmm0
-; CHECK-NEXT: retq
+; SSE2-LABEL: test_buildvector_v4i32_partial:
+; SSE2: # BB#0:
+; SSE2-NEXT: movd %edi, %xmm0
+; SSE2-NEXT: movd %esi, %xmm1
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
+; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: test_buildvector_v4i32_partial:
+; SSE41: # BB#0:
+; SSE41-NEXT: movd %edi, %xmm0
+; SSE41-NEXT: pinsrd $3, %esi, %xmm0
+; SSE41-NEXT: retq
%ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0
%ins1 = insertelement <4 x i32> %ins0, i32 undef, i32 1
%ins2 = insertelement <4 x i32> %ins1, i32 undef, i32 2
@@ -156,17 +226,36 @@ define <4 x i32> @test_buildvector_v4i32
}
define <8 x i16> @test_buildvector_v8i16_register(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) {
-; CHECK-LABEL: test_buildvector_v8i16_register:
-; CHECK: # BB#0:
-; CHECK-NEXT: movd %edi, %xmm0
-; CHECK-NEXT: pinsrw $1, %esi, %xmm0
-; CHECK-NEXT: pinsrw $2, %edx, %xmm0
-; CHECK-NEXT: pinsrw $3, %ecx, %xmm0
-; CHECK-NEXT: pinsrw $4, %r8d, %xmm0
-; CHECK-NEXT: pinsrw $5, %r9d, %xmm0
-; CHECK-NEXT: pinsrw $6, {{[0-9]+}}(%rsp), %xmm0
-; CHECK-NEXT: pinsrw $7, {{[0-9]+}}(%rsp), %xmm0
-; CHECK-NEXT: retq
+; SSE2-LABEL: test_buildvector_v8i16_register:
+; SSE2: # BB#0:
+; SSE2-NEXT: movd %ecx, %xmm0
+; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; SSE2-NEXT: movd %r9d, %xmm1
+; SSE2-NEXT: movd %esi, %xmm2
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
+; SSE2-NEXT: movd %edx, %xmm1
+; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; SSE2-NEXT: movd %r8d, %xmm3
+; SSE2-NEXT: movd %edi, %xmm0
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: test_buildvector_v8i16_register:
+; SSE41: # BB#0:
+; SSE41-NEXT: movd %edi, %xmm0
+; SSE41-NEXT: pinsrw $1, %esi, %xmm0
+; SSE41-NEXT: pinsrw $2, %edx, %xmm0
+; SSE41-NEXT: pinsrw $3, %ecx, %xmm0
+; SSE41-NEXT: pinsrw $4, %r8d, %xmm0
+; SSE41-NEXT: pinsrw $5, %r9d, %xmm0
+; SSE41-NEXT: pinsrw $6, {{[0-9]+}}(%rsp), %xmm0
+; SSE41-NEXT: pinsrw $7, {{[0-9]+}}(%rsp), %xmm0
+; SSE41-NEXT: retq
%ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0
%ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1
%ins2 = insertelement <8 x i16> %ins1, i16 %a2, i32 2
@@ -238,25 +327,60 @@ define <8 x i16> @test_buildvector_v8i16
}
define <16 x i8> @test_buildvector_v16i8_register(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15) {
-; CHECK-LABEL: test_buildvector_v16i8_register:
-; CHECK: # BB#0:
-; CHECK-NEXT: movd %edi, %xmm0
-; CHECK-NEXT: pinsrb $1, %esi, %xmm0
-; CHECK-NEXT: pinsrb $2, %edx, %xmm0
-; CHECK-NEXT: pinsrb $3, %ecx, %xmm0
-; CHECK-NEXT: pinsrb $4, %r8d, %xmm0
-; CHECK-NEXT: pinsrb $5, %r9d, %xmm0
-; CHECK-NEXT: pinsrb $6, {{[0-9]+}}(%rsp), %xmm0
-; CHECK-NEXT: pinsrb $7, {{[0-9]+}}(%rsp), %xmm0
-; CHECK-NEXT: pinsrb $8, {{[0-9]+}}(%rsp), %xmm0
-; CHECK-NEXT: pinsrb $9, {{[0-9]+}}(%rsp), %xmm0
-; CHECK-NEXT: pinsrb $10, {{[0-9]+}}(%rsp), %xmm0
-; CHECK-NEXT: pinsrb $11, {{[0-9]+}}(%rsp), %xmm0
-; CHECK-NEXT: pinsrb $12, {{[0-9]+}}(%rsp), %xmm0
-; CHECK-NEXT: pinsrb $13, {{[0-9]+}}(%rsp), %xmm0
-; CHECK-NEXT: pinsrb $14, {{[0-9]+}}(%rsp), %xmm0
-; CHECK-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0
-; CHECK-NEXT: retq
+; SSE2-LABEL: test_buildvector_v16i8_register:
+; SSE2: # BB#0:
+; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
+; SSE2-NEXT: movd %ecx, %xmm0
+; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; SSE2-NEXT: movd %r9d, %xmm1
+; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; SSE2-NEXT: movd %esi, %xmm2
+; SSE2-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1],xmm2[2],xmm3[2],xmm2[3],xmm3[3],xmm2[4],xmm3[4],xmm2[5],xmm3[5],xmm2[6],xmm3[6],xmm2[7],xmm3[7]
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
+; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
+; SSE2-NEXT: movd %edx, %xmm3
+; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7]
+; SSE2-NEXT: movd %r8d, %xmm1
+; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
+; SSE2-NEXT: movd %edi, %xmm0
+; SSE2-NEXT: movd {{.*#+}} xmm4 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7]
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: test_buildvector_v16i8_register:
+; SSE41: # BB#0:
+; SSE41-NEXT: movd %edi, %xmm0
+; SSE41-NEXT: pinsrb $1, %esi, %xmm0
+; SSE41-NEXT: pinsrb $2, %edx, %xmm0
+; SSE41-NEXT: pinsrb $3, %ecx, %xmm0
+; SSE41-NEXT: pinsrb $4, %r8d, %xmm0
+; SSE41-NEXT: pinsrb $5, %r9d, %xmm0
+; SSE41-NEXT: pinsrb $6, {{[0-9]+}}(%rsp), %xmm0
+; SSE41-NEXT: pinsrb $7, {{[0-9]+}}(%rsp), %xmm0
+; SSE41-NEXT: pinsrb $8, {{[0-9]+}}(%rsp), %xmm0
+; SSE41-NEXT: pinsrb $9, {{[0-9]+}}(%rsp), %xmm0
+; SSE41-NEXT: pinsrb $10, {{[0-9]+}}(%rsp), %xmm0
+; SSE41-NEXT: pinsrb $11, {{[0-9]+}}(%rsp), %xmm0
+; SSE41-NEXT: pinsrb $12, {{[0-9]+}}(%rsp), %xmm0
+; SSE41-NEXT: pinsrb $13, {{[0-9]+}}(%rsp), %xmm0
+; SSE41-NEXT: pinsrb $14, {{[0-9]+}}(%rsp), %xmm0
+; SSE41-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0
+; SSE41-NEXT: retq
%ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0
%ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1
%ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2
@@ -277,15 +401,31 @@ define <16 x i8> @test_buildvector_v16i8
}
define <16 x i8> @test_buildvector_v16i8_partial(i8 %a2, i8 %a6, i8 %a8, i8 %a11, i8 %a12, i8 %a15) {
-; CHECK-LABEL: test_buildvector_v16i8_partial:
-; CHECK: # BB#0:
-; CHECK-NEXT: pinsrb $2, %edi, %xmm0
-; CHECK-NEXT: pinsrb $6, %esi, %xmm0
-; CHECK-NEXT: pinsrb $8, %edx, %xmm0
-; CHECK-NEXT: pinsrb $11, %ecx, %xmm0
-; CHECK-NEXT: pinsrb $12, %r8d, %xmm0
-; CHECK-NEXT: pinsrb $15, %r9d, %xmm0
-; CHECK-NEXT: retq
+; SSE2-LABEL: test_buildvector_v16i8_partial:
+; SSE2: # BB#0:
+; SSE2-NEXT: movzbl %dil, %eax
+; SSE2-NEXT: pinsrw $1, %eax, %xmm0
+; SSE2-NEXT: movzbl %sil, %eax
+; SSE2-NEXT: pinsrw $3, %eax, %xmm0
+; SSE2-NEXT: movzbl %dl, %eax
+; SSE2-NEXT: pinsrw $4, %eax, %xmm0
+; SSE2-NEXT: shll $8, %ecx
+; SSE2-NEXT: pinsrw $5, %ecx, %xmm0
+; SSE2-NEXT: movzbl %r8b, %eax
+; SSE2-NEXT: pinsrw $6, %eax, %xmm0
+; SSE2-NEXT: shll $8, %r9d
+; SSE2-NEXT: pinsrw $7, %r9d, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: test_buildvector_v16i8_partial:
+; SSE41: # BB#0:
+; SSE41-NEXT: pinsrb $2, %edi, %xmm0
+; SSE41-NEXT: pinsrb $6, %esi, %xmm0
+; SSE41-NEXT: pinsrb $8, %edx, %xmm0
+; SSE41-NEXT: pinsrb $11, %ecx, %xmm0
+; SSE41-NEXT: pinsrb $12, %r8d, %xmm0
+; SSE41-NEXT: pinsrb $15, %r9d, %xmm0
+; SSE41-NEXT: retq
%ins0 = insertelement <16 x i8> undef, i8 undef, i32 0
%ins1 = insertelement <16 x i8> %ins0, i8 undef, i32 1
%ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2
@@ -306,17 +446,37 @@ define <16 x i8> @test_buildvector_v16i8
}
define <16 x i8> @test_buildvector_v16i8_register_zero(i8 %a0, i8 %a4, i8 %a6, i8 %a8, i8 %a11, i8 %a12, i8 %a15) {
-; CHECK-LABEL: test_buildvector_v16i8_register_zero:
-; CHECK: # BB#0:
-; CHECK-NEXT: pxor %xmm0, %xmm0
-; CHECK-NEXT: pinsrb $0, %edi, %xmm0
-; CHECK-NEXT: pinsrb $4, %esi, %xmm0
-; CHECK-NEXT: pinsrb $6, %edx, %xmm0
-; CHECK-NEXT: pinsrb $8, %ecx, %xmm0
-; CHECK-NEXT: pinsrb $11, %r8d, %xmm0
-; CHECK-NEXT: pinsrb $12, %r9d, %xmm0
-; CHECK-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0
-; CHECK-NEXT: retq
+; SSE2-LABEL: test_buildvector_v16i8_register_zero:
+; SSE2: # BB#0:
+; SSE2-NEXT: movzbl %dil, %eax
+; SSE2-NEXT: pxor %xmm0, %xmm0
+; SSE2-NEXT: pinsrw $0, %eax, %xmm0
+; SSE2-NEXT: movzbl %sil, %eax
+; SSE2-NEXT: pinsrw $2, %eax, %xmm0
+; SSE2-NEXT: movzbl %dl, %eax
+; SSE2-NEXT: pinsrw $3, %eax, %xmm0
+; SSE2-NEXT: movzbl %cl, %eax
+; SSE2-NEXT: pinsrw $4, %eax, %xmm0
+; SSE2-NEXT: shll $8, %r8d
+; SSE2-NEXT: pinsrw $5, %r8d, %xmm0
+; SSE2-NEXT: movzbl %r9b, %eax
+; SSE2-NEXT: pinsrw $6, %eax, %xmm0
+; SSE2-NEXT: movl {{[0-9]+}}(%rsp), %eax
+; SSE2-NEXT: shll $8, %eax
+; SSE2-NEXT: pinsrw $7, %eax, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: test_buildvector_v16i8_register_zero:
+; SSE41: # BB#0:
+; SSE41-NEXT: pxor %xmm0, %xmm0
+; SSE41-NEXT: pinsrb $0, %edi, %xmm0
+; SSE41-NEXT: pinsrb $4, %esi, %xmm0
+; SSE41-NEXT: pinsrb $6, %edx, %xmm0
+; SSE41-NEXT: pinsrb $8, %ecx, %xmm0
+; SSE41-NEXT: pinsrb $11, %r8d, %xmm0
+; SSE41-NEXT: pinsrb $12, %r9d, %xmm0
+; SSE41-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0
+; SSE41-NEXT: retq
%ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0
%ins1 = insertelement <16 x i8> %ins0, i8 0, i32 1
%ins2 = insertelement <16 x i8> %ins1, i8 0, i32 2
@@ -337,17 +497,37 @@ define <16 x i8> @test_buildvector_v16i8
}
define <16 x i8> @test_buildvector_v16i8_register_zero_2(i8 %a2, i8 %a3, i8 %a6, i8 %a8, i8 %a11, i8 %a12, i8 %a15) {
-; CHECK-LABEL: test_buildvector_v16i8_register_zero_2:
-; CHECK: # BB#0:
-; CHECK-NEXT: pxor %xmm0, %xmm0
-; CHECK-NEXT: pinsrb $2, %edi, %xmm0
-; CHECK-NEXT: pinsrb $3, %esi, %xmm0
-; CHECK-NEXT: pinsrb $6, %edx, %xmm0
-; CHECK-NEXT: pinsrb $8, %ecx, %xmm0
-; CHECK-NEXT: pinsrb $11, %r8d, %xmm0
-; CHECK-NEXT: pinsrb $12, %r9d, %xmm0
-; CHECK-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0
-; CHECK-NEXT: retq
+; SSE2-LABEL: test_buildvector_v16i8_register_zero_2:
+; SSE2: # BB#0:
+; SSE2-NEXT: shll $8, %esi
+; SSE2-NEXT: movzbl %dil, %eax
+; SSE2-NEXT: orl %esi, %eax
+; SSE2-NEXT: pxor %xmm0, %xmm0
+; SSE2-NEXT: pinsrw $1, %eax, %xmm0
+; SSE2-NEXT: movzbl %dl, %eax
+; SSE2-NEXT: pinsrw $3, %eax, %xmm0
+; SSE2-NEXT: movzbl %cl, %eax
+; SSE2-NEXT: pinsrw $4, %eax, %xmm0
+; SSE2-NEXT: shll $8, %r8d
+; SSE2-NEXT: pinsrw $5, %r8d, %xmm0
+; SSE2-NEXT: movzbl %r9b, %eax
+; SSE2-NEXT: pinsrw $6, %eax, %xmm0
+; SSE2-NEXT: movl {{[0-9]+}}(%rsp), %eax
+; SSE2-NEXT: shll $8, %eax
+; SSE2-NEXT: pinsrw $7, %eax, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: test_buildvector_v16i8_register_zero_2:
+; SSE41: # BB#0:
+; SSE41-NEXT: pxor %xmm0, %xmm0
+; SSE41-NEXT: pinsrb $2, %edi, %xmm0
+; SSE41-NEXT: pinsrb $3, %esi, %xmm0
+; SSE41-NEXT: pinsrb $6, %edx, %xmm0
+; SSE41-NEXT: pinsrb $8, %ecx, %xmm0
+; SSE41-NEXT: pinsrb $11, %r8d, %xmm0
+; SSE41-NEXT: pinsrb $12, %r9d, %xmm0
+; SSE41-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0
+; SSE41-NEXT: retq
%ins0 = insertelement <16 x i8> undef, i8 0, i32 0
%ins1 = insertelement <16 x i8> %ins0, i8 0, i32 1
%ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2
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