[PATCH] D29587: [DAGCombiner] mulhi + 1 never overflow.

[Amaury SECHET via Phabricator via llvm-commits]

deadalnix added a comment.

There is a nice small test case in adde-carry.ll , but it needs https://reviews.llvm.org/D29528 in addition to that one to trigger.



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Comment at: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2779
+  // mulhi + 1 never overflow
+  if (N0.getOpcode() == ISD::UMUL_LOHI &&
+      (~N1Zero & 0x01) == ~N1Zero)
----------------
efriedma wrote:
> Missing a check for which result you're using from the UMUL_LOHI.  (I think this transform is only valid for the high result.)
You are absolutely right.


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Comment at: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2780
+  if (N0.getOpcode() == ISD::UMUL_LOHI &&
+      (~N1Zero & 0x01) == ~N1Zero)
+    return OFK_Never;
----------------
efriedma wrote:
> Could you just write this as "~N1Zero == 1"?
I was wondering if I should match 0 or not. I went for the safe road and matched 0.


https://reviews.llvm.org/D29587