[PATCH] D29521: Add ADDC to SelectionDAG::computeKnownBits and ComputeNumSignBits.
Amaury SECHET via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 6 07:10:29 PST 2017
This revision was automatically updated to reflect the committed changes.
Closed by commit rL294188: Add ADDC to SelectionDAG::computeKnownBits and ComputeNumSignBits. (authored by deadalnix).
Changed prior to commit:
https://reviews.llvm.org/D29521?vs=87221&id=87227#toc
Repository:
rL LLVM
https://reviews.llvm.org/D29521
Files:
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/test/CodeGen/X86/known-bits.ll
Index: llvm/trunk/test/CodeGen/X86/known-bits.ll
===================================================================
--- llvm/trunk/test/CodeGen/X86/known-bits.ll
+++ llvm/trunk/test/CodeGen/X86/known-bits.ll
@@ -138,10 +138,9 @@
; X32-NEXT: adcl $0, %ecx
; X32-NEXT: shldl $22, %edx, %ecx
; X32-NEXT: shldl $22, %esi, %edx
-; X32-NEXT: shll $22, %esi
-; X32-NEXT: movl %esi, 4(%eax)
; X32-NEXT: movl %edx, 8(%eax)
; X32-NEXT: movl %ecx, 12(%eax)
+; X32-NEXT: movl $0, 4(%eax)
; X32-NEXT: movl $0, (%eax)
; X32-NEXT: popl %esi
; X32-NEXT: popl %edi
@@ -155,8 +154,7 @@
; X64-NEXT: sbbq %rax, %rax
; X64-NEXT: subl %eax, %edx
; X64-NEXT: shldq $54, %rsi, %rdx
-; X64-NEXT: shlq $54, %rsi
-; X64-NEXT: movq %rsi, %rax
+; X64-NEXT: xorl %eax, %eax
; X64-NEXT: retq
%1 = and i64 %a0, -1024
%2 = zext i64 %1 to i128
Index: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2506,6 +2506,7 @@
LLVM_FALLTHROUGH;
}
case ISD::ADD:
+ case ISD::ADDC:
case ISD::ADDE: {
// Output known-0 bits are known if clear or set in both the low clear bits
// common to both LHS & RHS. For example, 8+(X<<3) is known to have the
@@ -2526,7 +2527,7 @@
KnownZeroLow = std::min(KnownZeroLow,
KnownZero2.countTrailingOnes());
- if (Opcode == ISD::ADD) {
+ if (Opcode == ISD::ADD || Opcode == ISD::ADDC) {
KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroLow);
if (KnownZeroHigh > 1)
KnownZero |= APInt::getHighBitsSet(BitWidth, KnownZeroHigh - 1);
@@ -2945,6 +2946,7 @@
}
break;
case ISD::ADD:
+ case ISD::ADDC:
// Add can have at most one carry bit. Thus we know that the output
// is, at worst, one more bit than the inputs.
Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
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