[llvm] r294188 - Add ADDC to SelectionDAG::computeKnownBits and ComputeNumSignBits.

[Amaury Sechet via llvm-commits]

Author: deadalnix
Date: Mon Feb  6 08:59:06 2017
New Revision: 294188

URL: http://llvm.org/viewvc/llvm-project?rev=294188&view=rev
Log:
Add ADDC to SelectionDAG::computeKnownBits and ComputeNumSignBits.

Summary: As per title.

Reviewers: bkramer, sunfish, lattner, RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D29521

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/test/CodeGen/X86/known-bits.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=294188&r1=294187&r2=294188&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Feb  6 08:59:06 2017
@@ -2506,6 +2506,7 @@ void SelectionDAG::computeKnownBits(SDVa
     LLVM_FALLTHROUGH;
   }
   case ISD::ADD:
+  case ISD::ADDC:
   case ISD::ADDE: {
     // Output known-0 bits are known if clear or set in both the low clear bits
     // common to both LHS & RHS.  For example, 8+(X<<3) is known to have the
@@ -2526,7 +2527,7 @@ void SelectionDAG::computeKnownBits(SDVa
     KnownZeroLow = std::min(KnownZeroLow,
                             KnownZero2.countTrailingOnes());
 
-    if (Opcode == ISD::ADD) {
+    if (Opcode == ISD::ADD || Opcode == ISD::ADDC) {
       KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroLow);
       if (KnownZeroHigh > 1)
         KnownZero |= APInt::getHighBitsSet(BitWidth, KnownZeroHigh - 1);
@@ -2945,6 +2946,7 @@ unsigned SelectionDAG::ComputeNumSignBit
     }
     break;
   case ISD::ADD:
+  case ISD::ADDC:
     // Add can have at most one carry bit.  Thus we know that the output
     // is, at worst, one more bit than the inputs.
     Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);

Modified: llvm/trunk/test/CodeGen/X86/known-bits.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/known-bits.ll?rev=294188&r1=294187&r2=294188&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/known-bits.ll (original)
+++ llvm/trunk/test/CodeGen/X86/known-bits.ll Mon Feb  6 08:59:06 2017
@@ -138,10 +138,9 @@ define i128 @knownbits_mask_addc_shl(i64
 ; X32-NEXT:    adcl $0, %ecx
 ; X32-NEXT:    shldl $22, %edx, %ecx
 ; X32-NEXT:    shldl $22, %esi, %edx
-; X32-NEXT:    shll $22, %esi
-; X32-NEXT:    movl %esi, 4(%eax)
 ; X32-NEXT:    movl %edx, 8(%eax)
 ; X32-NEXT:    movl %ecx, 12(%eax)
+; X32-NEXT:    movl $0, 4(%eax)
 ; X32-NEXT:    movl $0, (%eax)
 ; X32-NEXT:    popl %esi
 ; X32-NEXT:    popl %edi
@@ -155,8 +154,7 @@ define i128 @knownbits_mask_addc_shl(i64
 ; X64-NEXT:    sbbq %rax, %rax
 ; X64-NEXT:    subl %eax, %edx
 ; X64-NEXT:    shldq $54, %rsi, %rdx
-; X64-NEXT:    shlq $54, %rsi
-; X64-NEXT:    movq %rsi, %rax
+; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    retq
   %1 = and i64 %a0, -1024
   %2 = zext i64 %1 to i128