[PATCH] D29219: [AArch64][TableGen] Skip tied result operands for InstAlias

[Graham Hunter via Phabricator via llvm-commits]

huntergr added a comment.

In https://reviews.llvm.org/D29219#667645, @rengolin wrote:

> In https://reviews.llvm.org/D29219#667592, @huntergr wrote:
>
> > Ping.
>
>
> Hi Graham,
>
> I was waiting from other comments, especially regarding the tied operand logic for other targets, which I'm not familiar with. I'm surprised this didn't trigger anything else in any other target. Are you building and testing all targets?


I've run make check-all for all targets, no failures; I was a little surprised that no changes were required on other targets as well (with both debug and release builds), but I don't know how many other architectures have significant differences between representations of the same instruction.

> 
> 
>> For clarity wrt. the movk/bic/orr pattern changes, they never triggered when printing asm before because the base patterns in AArch64InstrFormats.td (BaseInsertImmediate and BaseSIMDModifiedImmVectorTied) both contain tied register constraints. Since they now print with this change, I've adjusted the priority where needed to avoid breaking the existing unit tests, and just change ins to mov.
> 
> I suspected as much. It looks good from the AArch64 point of view. We can give it a few more days, and if no one objects, I'll approve and we try our luck on the buildbots. :)
> 
> cheers,
> --renato




https://reviews.llvm.org/D29219