[PATCH] D29219: [AArch64][TableGen] Skip tied result operands for InstAlias

[Graham Hunter via Phabricator via llvm-commits]

huntergr added a comment.

Ping.

For clarity wrt. the movk/bic/orr pattern changes, they never triggered when printing asm before because the base patterns in AArch64InstrFormats.td (BaseInsertImmediate and BaseSIMDModifiedImmVectorTied) both contain tied register constraints. Since they now print with this change, I've adjusted the priority where needed to avoid breaking the existing unit tests, and just change ins to mov.


https://reviews.llvm.org/D29219