[llvm] r294132 - [X86] Fix printing of sha256rnds2 to include the implicit %xmm0 argument.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Sun Feb  5 12:33:31 2017
New Revision: 294132

URL: http://llvm.org/viewvc/llvm-project?rev=294132&view=rev
Log:
[X86] Fix printing of sha256rnds2 to include the implicit %xmm0 argument.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/CodeGen/X86/sha.ll
    llvm/trunk/test/MC/Disassembler/X86/x86-64.txt
    llvm/trunk/test/MC/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=294132&r1=294131&r2=294132&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Feb  5 12:33:31 2017
@@ -7479,14 +7479,18 @@ multiclass SHAI_binop<bits<8> Opc, strin
                       bit UsesXMM0 = 0> {
   def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
              (ins VR128:$src1, VR128:$src2),
-             !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+             !if(UsesXMM0,
+                 !strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
+                 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
              [!if(UsesXMM0,
                   (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
                   (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
 
   def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
              (ins VR128:$src1, i128mem:$src2),
-             !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+             !if(UsesXMM0,
+                 !strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
+                 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
              [!if(UsesXMM0,
                   (set VR128:$dst, (IntId VR128:$src1,
                     (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
@@ -7521,10 +7525,10 @@ let Constraints = "$src1 = $dst", Predic
 }
 
 // Aliases with explicit %xmm0
-def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
-                (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
-def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
-                (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
+def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
+                (SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>;
+def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
+                (SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>;
 
 //===----------------------------------------------------------------------===//
 // AES-NI Instructions

Modified: llvm/trunk/test/CodeGen/X86/sha.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sha.ll?rev=294132&r1=294131&r2=294132&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sha.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sha.ll Sun Feb  5 12:33:31 2017
@@ -86,7 +86,7 @@ entry:
   ; CHECK: test_sha256rnds2rr
   ; CHECK: movaps %xmm0, [[XMM_TMP1:%xmm[1-9][0-9]?]]
   ; CHECK: movaps %xmm2, %xmm0
-  ; CHECK: sha256rnds2 %xmm1, [[XMM_TMP1]]
+  ; CHECK: sha256rnds2 %xmm0, %xmm1, [[XMM_TMP1]]
 }
 
 define <4 x i32> @test_sha256rnds2rm(<4 x i32> %a, <4 x i32>* %b, <4 x i32> %c) nounwind uwtable {
@@ -97,7 +97,7 @@ entry:
   ; CHECK: test_sha256rnds2rm
   ; CHECK: movaps %xmm0, [[XMM_TMP2:%xmm[1-9][0-9]?]]
   ; CHECK: movaps %xmm1, %xmm0
-  ; CHECK: sha256rnds2 (%rdi), [[XMM_TMP2]]
+  ; CHECK: sha256rnds2 %xmm0, (%rdi), [[XMM_TMP2]]
 }
 
 declare <4 x i32> @llvm.x86.sha256msg1(<4 x i32>, <4 x i32>) nounwind readnone
@@ -136,4 +136,4 @@ entry:
   ret <4 x i32> %1
   ; CHECK: test_sha256msg2rm
   ; CHECK: sha256msg2 (%rdi), %xmm0
-}
\ No newline at end of file
+}

Modified: llvm/trunk/test/MC/Disassembler/X86/x86-64.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-64.txt?rev=294132&r1=294131&r2=294132&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-64.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-64.txt Sun Feb  5 12:33:31 2017
@@ -185,10 +185,10 @@
 # CHECK: sha1msg2 (%rax), %xmm2
 0x0f 0x38 0xca 0x10
 
-# CHECK: sha256rnds2 (%rax), %xmm2
+# CHECK: sha256rnds2 %xmm0, (%rax), %xmm2
 0x0f 0x38 0xcb 0x10
 
-# CHECK: sha256rnds2 %xmm1, %xmm2
+# CHECK: sha256rnds2 %xmm0, %xmm1, %xmm2
 0x0f 0x38 0xcb 0xd1
 
 # CHECK: sha256msg1 %xmm1, %xmm2

Modified: llvm/trunk/test/MC/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_64-encoding.s?rev=294132&r1=294131&r2=294132&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/X86/x86_64-encoding.s Sun Feb  5 12:33:31 2017
@@ -148,19 +148,19 @@ sha1msg2 %xmm1, %xmm2
 // CHECK:   encoding: [0x0f,0x38,0xca,0x10]
 sha1msg2 (%rax), %xmm2
 
-// CHECK: sha256rnds2 (%rax), %xmm2
+// CHECK: sha256rnds2 %xmm0, (%rax), %xmm2
 // CHECK:   encoding: [0x0f,0x38,0xcb,0x10]
 sha256rnds2 (%rax), %xmm2
 
-// CHECK: sha256rnds2 %xmm1, %xmm2
+// CHECK: sha256rnds2 %xmm0, %xmm1, %xmm2
 // CHECK:   encoding: [0x0f,0x38,0xcb,0xd1]
 sha256rnds2 %xmm1, %xmm2
 
-// CHECK: sha256rnds2 (%rax), %xmm2
+// CHECK: sha256rnds2 %xmm0, (%rax), %xmm2
 // CHECK:   encoding: [0x0f,0x38,0xcb,0x10]
 sha256rnds2 %xmm0, (%rax), %xmm2
 
-// CHECK: sha256rnds2 %xmm1, %xmm2
+// CHECK: sha256rnds2 %xmm0, %xmm1, %xmm2
 // CHECK:   encoding: [0x0f,0x38,0xcb,0xd1]
 sha256rnds2 %xmm0, %xmm1, %xmm2