[PATCH] D29268: [DAGCombine] Combine composition of ADDC(ADDE)

[Zvi Rackover via Phabricator via llvm-commits]

zvi updated this revision to Diff 87147.
zvi added a comment.

Following @deadalnix's suggestion for special case where Y is all ones. Thanks!


Repository:
  rL LLVM

https://reviews.llvm.org/D29268

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/X86/adde-carry.ll


Index: test/CodeGen/X86/adde-carry.ll
===================================================================
--- test/CodeGen/X86/adde-carry.ll
+++ test/CodeGen/X86/adde-carry.ll
@@ -28,9 +28,7 @@
 ; CHECK-LABEL: pr31719:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addq %rdx, %rdi
-; CHECK-NEXT:    sbbq %rax, %rax
-; CHECK-NEXT:    andl $1, %eax
-; CHECK-NEXT:    addq %rsi, %rax
+; CHECK-NEXT:    adcq $0, %rsi
 ; CHECK-NEXT:    sbbq %rax, %rax
 ; CHECK-NEXT:    andl $1, %eax
 ; CHECK-NEXT:    retq
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1867,6 +1867,17 @@
                                    SDLoc(N), MVT::Glue));
   }
 
+  // (addc X, (adde Y, 0, Carry)) -> (adde X, Y, Carry) if Y + 1 cannot overflow
+  if (N1.getOpcode() == ISD::ADDE &&
+      N->isOnlyUserOf(N1.getValue(0).getNode()) &&
+      isNullConstant(N1.getOperand(1))) {
+    APInt YZero, YOne;
+    DAG.computeKnownBits(N1.getOperand(0), YZero, YOne);
+    if (YZero != 0)
+      return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(), N0,
+                         N1->getOperand(0), N1->getOperand(2));
+  }
+
   return SDValue();
 }
 


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