[PATCH] D29521: Add ADDC to SelectionDAG::computeKnownBits and ComputeNumSignBits.
Amaury SECHET via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 3 16:35:10 PST 2017
deadalnix created this revision.
As per title.
https://reviews.llvm.org/D29521
Files:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2506,6 +2506,7 @@
LLVM_FALLTHROUGH;
}
case ISD::ADD:
+ case ISD::ADDC:
case ISD::ADDE: {
// Output known-0 bits are known if clear or set in both the low clear bits
// common to both LHS & RHS. For example, 8+(X<<3) is known to have the
@@ -2526,7 +2527,7 @@
KnownZeroLow = std::min(KnownZeroLow,
KnownZero2.countTrailingOnes());
- if (Opcode == ISD::ADD) {
+ if (Opcode == ISD::ADD || Opcode == ISD::ADDC) {
KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroLow);
if (KnownZeroHigh > 1)
KnownZero |= APInt::getHighBitsSet(BitWidth, KnownZeroHigh - 1);
@@ -2924,6 +2925,7 @@
}
break;
case ISD::ADD:
+ case ISD::ADDC:
// Add can have at most one carry bit. Thus we know that the output
// is, at worst, one more bit than the inputs.
Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
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