[llvm] r293933 - [Hexagon] Adding opExtentBits and opExtentAlign to GPrel instructions
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 2 12:35:16 PST 2017
Author: kparzysz
Date: Thu Feb 2 14:35:12 2017
New Revision: 293933
URL: http://llvm.org/viewvc/llvm-project?rev=293933&view=rev
Log:
[Hexagon] Adding opExtentBits and opExtentAlign to GPrel instructions
Patch by Colin LeMahieu.
Modified:
llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
llvm/trunk/test/MC/Hexagon/relocations.s
Modified: llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=293933&r1=293932&r2=293933&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp Thu Feb 2 14:35:12 2017
@@ -1756,8 +1756,8 @@ int HexagonAsmParser::processInstruction
TmpInst.setOpcode(Hexagon::L2_loadrdgp);
TmpInst.addOperand(MO_0);
- TmpInst.addOperand(
- MCOperand::createExpr(MCSymbolRefExpr::create(Sym, getContext())));
+ TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
+ MCSymbolRefExpr::create(Sym, getContext()), getContext())));
Inst = TmpInst;
}
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=293933&r1=293932&r2=293933&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Thu Feb 2 14:35:12 2017
@@ -2543,6 +2543,14 @@ class T_StoreAbsGP <string mnemonic, Reg
!if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
!if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
/* u16_0Imm */ addr{15-0})));
+ let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
+ !if (!eq(ImmOpStr, "u16_2Imm"), 18,
+ !if (!eq(ImmOpStr, "u16_1Imm"), 17,
+ /* u16_0Imm */ 16)));
+ let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
+ !if (!eq(ImmOpStr, "u16_2Imm"), 2,
+ !if (!eq(ImmOpStr, "u16_1Imm"), 1,
+ /* u16_0Imm */ 0)));
// Store upper-half and store doubleword cannot be NV.
let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
let Uses = !if (isAbs, [], [GP]);
@@ -2651,6 +2659,14 @@ class T_StoreAbsGP_NV <string mnemonic,
!if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
!if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
/* u16_0Imm */ addr{15-0})));
+ let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
+ !if (!eq(ImmOpStr, "u16_2Imm"), 18,
+ !if (!eq(ImmOpStr, "u16_1Imm"), 17,
+ /* u16_0Imm */ 16)));
+ let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
+ !if (!eq(ImmOpStr, "u16_2Imm"), 2,
+ !if (!eq(ImmOpStr, "u16_1Imm"), 1,
+ /* u16_0Imm */ 0)));
let IClass = 0b0100;
let Inst{27} = 1;
@@ -2822,6 +2838,14 @@ class T_LoadAbsGP <string mnemonic, Regi
!if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
!if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
/* u16_0Imm */ addr{15-0})));
+ let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
+ !if (!eq(ImmOpStr, "u16_2Imm"), 18,
+ !if (!eq(ImmOpStr, "u16_1Imm"), 17,
+ /* u16_0Imm */ 16)));
+ let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
+ !if (!eq(ImmOpStr, "u16_2Imm"), 2,
+ !if (!eq(ImmOpStr, "u16_1Imm"), 1,
+ /* u16_0Imm */ 0)));
let IClass = 0b0100;
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp?rev=293933&r1=293932&r2=293933&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp Thu Feb 2 14:35:12 2017
@@ -521,7 +521,31 @@ unsigned HexagonMCCodeEmitter::getExprOp
if (HexagonMCInstrInfo::s23_2_reloc(*MO.getExpr()))
FixupKind = Hexagon::fixup_Hexagon_23_REG;
else
- raise_relocation_error(bits, kind);
+ if (MCID.mayStore() || MCID.mayLoad()) {
+ for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses;
+ ++ImpUses) {
+ if (*ImpUses != Hexagon::GP)
+ continue;
+ switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
+ case HexagonII::MemAccessSize::ByteAccess:
+ FixupKind = fixup_Hexagon_GPREL16_0;
+ break;
+ case HexagonII::MemAccessSize::HalfWordAccess:
+ FixupKind = fixup_Hexagon_GPREL16_1;
+ break;
+ case HexagonII::MemAccessSize::WordAccess:
+ FixupKind = fixup_Hexagon_GPREL16_2;
+ break;
+ case HexagonII::MemAccessSize::DoubleWordAccess:
+ FixupKind = fixup_Hexagon_GPREL16_3;
+ break;
+ default:
+ raise_relocation_error(bits, kind);
+ }
+ }
+ }
+ else
+ raise_relocation_error(bits, kind);
break;
}
case MCSymbolRefExpr::VK_DTPREL:
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp?rev=293933&r1=293932&r2=293933&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp Thu Feb 2 14:35:12 2017
@@ -707,6 +707,17 @@ bool HexagonMCInstrInfo::mustNotExtend(M
HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
return HExpr.mustNotExtend();
}
+void HexagonMCInstrInfo::setS23_2_reloc(MCExpr const &Expr, bool Val) {
+ HexagonMCExpr &HExpr =
+ const_cast<HexagonMCExpr &>(*llvm::cast<HexagonMCExpr>(&Expr));
+ HExpr.setS23_2_reloc(Val);
+}
+bool HexagonMCInstrInfo::s23_2_reloc(MCExpr const &Expr) {
+ HexagonMCExpr const *HExpr = llvm::dyn_cast<HexagonMCExpr>(&Expr);
+ if (!HExpr)
+ return false;
+ return HExpr->s23_2_reloc();
+}
void HexagonMCInstrInfo::padEndloop(MCContext &Context, MCInst &MCB) {
MCInst Nop;
@@ -772,15 +783,6 @@ void HexagonMCInstrInfo::setMemStoreReor
Operand.setImm(Operand.getImm() | memStoreReorderEnabledMask);
assert(isMemStoreReorderEnabled(MCI));
}
-void HexagonMCInstrInfo::setS23_2_reloc(MCExpr const &Expr, bool Val) {
- HexagonMCExpr &HExpr =
- const_cast<HexagonMCExpr &>(*llvm::cast<HexagonMCExpr>(&Expr));
- HExpr.setS23_2_reloc(Val);
-}
-bool HexagonMCInstrInfo::s23_2_reloc(MCExpr const &Expr) {
- HexagonMCExpr const &HExpr = *llvm::cast<HexagonMCExpr>(&Expr);
- return HExpr.s23_2_reloc();
-}
void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) {
assert(isBundle(MCI));
Modified: llvm/trunk/test/MC/Hexagon/relocations.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/relocations.s?rev=293933&r1=293932&r2=293933&view=diff
==============================================================================
--- llvm/trunk/test/MC/Hexagon/relocations.s (original)
+++ llvm/trunk/test/MC/Hexagon/relocations.s Thu Feb 2 14:35:12 2017
@@ -30,19 +30,19 @@ r_hex_8:
# CHECK: R_HEX_GPREL16_0
r_hex_gprel16_0:
-{ r0 = memb (#undefined at gotrel) }
+{ r0 = memb (gp+#undefined) }
# CHECK: R_HEX_GPREL16_1
r_hex_gprel16_1:
-{ r0 = memh (#undefined at gotrel) }
+{ r0 = memh (gp+#undefined) }
# CHECK: R_HEX_GPREL16_2
r_hex_gprel16_2:
-{ r0 = memw (#undefined at gotrel) }
+{ r0 = memw (gp+#undefined) }
# CHECK: R_HEX_GPREL16_3
r_hex_gprel16_3:
-{ r1:0 = memd (#undefined at gotrel) }
+{ r1:0 = memd (gp+#undefined) }
# CHECK: R_HEX_B13_PCREL
r_hex_b13_pcrel:
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