[llvm] r293929 - [Hexagon] Remove A4_ext_* pseudo instructions
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 2 11:58:22 PST 2017
Author: kparzysz
Date: Thu Feb 2 13:58:22 2017
New Revision: 293929
URL: http://llvm.org/viewvc/llvm-project?rev=293929&view=rev
Log:
[Hexagon] Remove A4_ext_* pseudo instructions
Patch by Colin LeMahieu.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td?rev=293929&r1=293928&r2=293929&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td Thu Feb 2 13:58:22 2017
@@ -21,7 +21,7 @@ def TypeV4LDST : IType<9>;
def TypeNV : IType<10>;
def TypeDUPLEX : IType<11>;
def TypeCJ : IType<12>;
-def TypePREFIX : IType<30>;
+def TypeEXTENDER : IType<30>;
// Duplex Instruction Class Declaration
//===----------------------------------------------------------------------===//
@@ -141,7 +141,7 @@ class MEMInst_V4<dag outs, dag ins, stri
class EXTENDERInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
: InstHexagon<outs, ins, asmstr, pattern, "", EXTENDER_tc_1_SLOT0123,
- TypePREFIX>, OpcodeHexagon;
+ TypeEXTENDER>, OpcodeHexagon;
class SUBInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "">
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=293929&r1=293928&r2=293929&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Thu Feb 2 13:58:22 2017
@@ -42,13 +42,6 @@ class T_Immext<Operand ImmType>
}
def A4_ext : T_Immext<u26_6Imm>;
-let isCodeGenOnly = 1 in {
- let isBranch = 1 in
- def A4_ext_b : T_Immext<brtarget>;
- let isCall = 1 in
- def A4_ext_c : T_Immext<calltarget>;
- def A4_ext_g : T_Immext<globaladdress>;
-}
// Hexagon V4 Architecture spec defines 8 instruction classes:
// LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h?rev=293929&r1=293928&r2=293929&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h Thu Feb 2 13:58:22 2017
@@ -63,8 +63,8 @@ namespace HexagonII {
TypeCVI_VM_STU = 27,
TypeCVI_HIST = 28,
TypeCVI_LAST = TypeCVI_HIST,
- TypePREFIX = 30, // Such as extenders.
- TypeENDLOOP = 31 // Such as end of a HW loop.
+ TypeEXTENDER = 30,
+ TypeENDLOOP = 31 // Such as end of a HW loop.
};
enum SubTarget {
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp?rev=293929&r1=293928&r2=293929&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp Thu Feb 2 13:58:22 2017
@@ -122,10 +122,9 @@ void HexagonMCCodeEmitter::EncodeSingleI
Binary = getBinaryCodeForInstr(MI, Fixups, STI);
// Check for unimplemented instructions. Immediate extenders
// are encoded as zero, so they need to be accounted for.
- if ((!Binary) &&
- ((MI.getOpcode() != DuplexIClass0) && (MI.getOpcode() != A4_ext) &&
- (MI.getOpcode() != A4_ext_b) && (MI.getOpcode() != A4_ext_c) &&
- (MI.getOpcode() != A4_ext_g))) {
+ if (!Binary &&
+ MI.getOpcode() != DuplexIClass0 &&
+ MI.getOpcode() != A4_ext) {
DEBUG(dbgs() << "Unimplemented inst: "
" `" << HexagonMCInstrInfo::getName(MCII, MI) << "'"
"\n");
@@ -226,14 +225,13 @@ void raise_relocation_error(unsigned bit
/// getFixupNoBits - Some insns are not extended and thus have no
/// bits. These cases require a more brute force method for determining
/// the correct relocation.
-namespace {
-Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
- const MCOperand &MO,
- const MCSymbolRefExpr::VariantKind kind) {
+Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits(
+ MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO,
+ const MCSymbolRefExpr::VariantKind kind) const {
const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI);
- if (insnType == HexagonII::TypePREFIX) {
+ if (insnType == HexagonII::TypeEXTENDER) {
switch (kind) {
case MCSymbolRefExpr::VK_GOTREL:
return Hexagon::fixup_Hexagon_GOTREL_32_6_X;
@@ -252,11 +250,19 @@ Hexagon::Fixups getFixupNoBits(MCInstrIn
case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
return Hexagon::fixup_Hexagon_IE_GOT_32_6_X;
case MCSymbolRefExpr::VK_Hexagon_PCREL:
- case MCSymbolRefExpr::VK_None:
- if (MCID.isBranch())
- return Hexagon::fixup_Hexagon_B32_PCREL_X;
- else
- return Hexagon::fixup_Hexagon_32_6_X;
+ return Hexagon::fixup_Hexagon_B32_PCREL_X;
+ case MCSymbolRefExpr::VK_None: {
+ auto Insts = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
+ for (auto I = Insts.begin(), N = Insts.end(); I != N; ++I)
+ if (I->getInst() == &MI) {
+ if (HexagonMCInstrInfo::getDesc(MCII, *(I + 1)->getInst()).isBranch() ||
+ (HexagonMCInstrInfo::getType(MCII, *(I + 1)->getInst()) == HexagonII::TypeCR))
+ return Hexagon::fixup_Hexagon_B32_PCREL_X;
+ else
+ return Hexagon::fixup_Hexagon_32_6_X;
+ }
+ raise_relocation_error(0, kind);
+ }
default:
raise_relocation_error(0, kind);
}
@@ -339,7 +345,6 @@ Hexagon::Fixups getFixupNoBits(MCInstrIn
}
llvm_unreachable("Relocation exit not taken");
}
-}
namespace llvm {
extern const MCInstrDesc HexagonInsts[];
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h?rev=293929&r1=293928&r2=293929&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h Thu Feb 2 13:58:22 2017
@@ -15,6 +15,7 @@
#ifndef HEXAGONMCCODEEMITTER_H
#define HEXAGONMCCODEEMITTER_H
+#include "MCTargetDesc/HexagonFixupKinds.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
@@ -38,6 +39,10 @@ class HexagonMCCodeEmitter : public MCCo
const MCExpr *ME, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
+ Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
+ const MCOperand &MO,
+ const MCSymbolRefExpr::VariantKind kind) const;
+
public:
HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCContext &aMCT);
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp?rev=293929&r1=293928&r2=293929&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp Thu Feb 2 13:58:22 2017
@@ -131,12 +131,8 @@ MCInst HexagonMCInstrInfo::deriveExtende
assert(HexagonMCInstrInfo::isExtendable(MCII, Inst) ||
HexagonMCInstrInfo::isExtended(MCII, Inst));
- MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst);
MCInst XMI;
- XMI.setOpcode((Desc.isBranch() || Desc.isCall() ||
- HexagonMCInstrInfo::getType(MCII, Inst) == HexagonII::TypeCR)
- ? Hexagon::A4_ext_b
- : Hexagon::A4_ext);
+ XMI.setOpcode(Hexagon::A4_ext);
if (MO.isImm())
XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
else if (MO.isExpr())
@@ -510,9 +506,7 @@ bool HexagonMCInstrInfo::isFloat(MCInstr
}
bool HexagonMCInstrInfo::isImmext(MCInst const &MCI) {
- auto Op = MCI.getOpcode();
- return (Op == Hexagon::A4_ext_b || Op == Hexagon::A4_ext_c ||
- Op == Hexagon::A4_ext_g || Op == Hexagon::A4_ext);
+ return MCI.getOpcode() == Hexagon::A4_ext;
}
bool HexagonMCInstrInfo::isInnerLoop(MCInst const &MCI) {
@@ -558,6 +552,10 @@ bool HexagonMCInstrInfo::isPredicated(MC
return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
}
+bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
+ return HexagonII::TypeEXTENDER == HexagonMCInstrInfo::getType(MCII, MCI);
+}
+
bool HexagonMCInstrInfo::isPredicateLate(MCInstrInfo const &MCII,
MCInst const &MCI) {
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
@@ -582,10 +580,6 @@ bool HexagonMCInstrInfo::isPredReg(unsig
return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
}
-bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
- return (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypePREFIX);
-}
-
bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
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