[PATCH] D29448: [RegAlloc] Don’t freeze reserved registers again if it is not necessary

[Volkan Keles via Phabricator via llvm-commits]

volkan created this revision.
Herald added subscribers: nemanjai, MatzeB.

SelectionDAGISel calls MachineRegisterInfo::freezeReservedRegs
right after ISel and MachineRegisterInfo caches the reserved registers
vector. However, RegAlloc calls the same function again before the
allocation process. This might be expensive if the target has a large
number of registers.

The second call was removed in r168630 in 2012, but it caused a few
failures and got reverted. They don’t fail right now, but there are 4
PowerPC tests failing. So, it seems some targets still need to update
the reserved registers before RegAlloc.
Failing Tests (4):

  LLVM :: CodeGen/PowerPC/ppc64-anyregcc-crash.ll
  LLVM :: CodeGen/PowerPC/ppc64-anyregcc.ll
  LLVM :: CodeGen/PowerPC/ppc64-patchpoint.ll
  LLVM :: CodeGen/PowerPC/ppc64-stackmap.ll


https://reviews.llvm.org/D29448

Files:
  include/llvm/Target/TargetRegisterInfo.h
  lib/CodeGen/RegAllocBase.cpp
  lib/CodeGen/RegAllocFast.cpp
  lib/CodeGen/RegAllocPBQP.cpp
  lib/Target/PowerPC/PPCRegisterInfo.h


Index: lib/Target/PowerPC/PPCRegisterInfo.h
===================================================================
--- lib/Target/PowerPC/PPCRegisterInfo.h
+++ lib/Target/PowerPC/PPCRegisterInfo.h
@@ -101,6 +101,11 @@
     return true;
   }
 
+  bool requiresFreezingReservedRegsBeforeRegAlloc(
+      const MachineFunction &MF) const override {
+    return true;
+  }
+
   void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
   void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const;
   void lowerCRSpilling(MachineBasicBlock::iterator II,
Index: lib/CodeGen/RegAllocPBQP.cpp
===================================================================
--- lib/CodeGen/RegAllocPBQP.cpp
+++ lib/CodeGen/RegAllocPBQP.cpp
@@ -753,7 +753,9 @@
 
   std::unique_ptr<Spiller> VRegSpiller(createInlineSpiller(*this, MF, VRM));
 
-  MF.getRegInfo().freezeReservedRegs(MF);
+  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
+  if (TRI->requiresFreezingReservedRegsBeforeRegAlloc(MF))
+    MF.getRegInfo().freezeReservedRegs(MF);
 
   DEBUG(dbgs() << "PBQP Register Allocating for " << MF.getName() << "\n");
 
Index: lib/CodeGen/RegAllocFast.cpp
===================================================================
--- lib/CodeGen/RegAllocFast.cpp
+++ lib/CodeGen/RegAllocFast.cpp
@@ -1091,7 +1091,8 @@
   MRI = &MF->getRegInfo();
   TRI = MF->getSubtarget().getRegisterInfo();
   TII = MF->getSubtarget().getInstrInfo();
-  MRI->freezeReservedRegs(Fn);
+  if (TRI->requiresFreezingReservedRegsBeforeRegAlloc(Fn))
+    MRI->freezeReservedRegs(Fn);
   RegClassInfo.runOnMachineFunction(Fn);
   UsedInInstr.clear();
   UsedInInstr.setUniverse(TRI->getNumRegUnits());
Index: lib/CodeGen/RegAllocBase.cpp
===================================================================
--- lib/CodeGen/RegAllocBase.cpp
+++ lib/CodeGen/RegAllocBase.cpp
@@ -60,8 +60,10 @@
   VRM = &vrm;
   LIS = &lis;
   Matrix = &mat;
-  MRI->freezeReservedRegs(vrm.getMachineFunction());
-  RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
+  MachineFunction &MF = VRM->getMachineFunction();
+  if (TRI->requiresFreezingReservedRegsBeforeRegAlloc(MF))
+    MRI->freezeReservedRegs(MF);
+  RegClassInfo.runOnMachineFunction(MF);
 }
 
 // Visit all the live registers. If they are already assigned to a physical
Index: include/llvm/Target/TargetRegisterInfo.h
===================================================================
--- include/llvm/Target/TargetRegisterInfo.h
+++ include/llvm/Target/TargetRegisterInfo.h
@@ -818,6 +818,13 @@
     return false;
   }
 
+  /// Returns true if the target wants to update the reserved register
+  /// before the register allocation process.
+  virtual bool
+  requiresFreezingReservedRegsBeforeRegAlloc(const MachineFunction &MF) const {
+    return false;
+  }
+
   /// Return true if target has reserved a spill slot in the stack frame of
   /// the given function for the specified register. e.g. On x86, if the frame
   /// register is required, the first fixed stack object is reserved as its


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D29448.86796.patch
Type: text/x-patch
Size: 3040 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170202/20a46020/attachment.bin>