[PATCH] D29177: [PowerPC][Altivec] Add mfvrd extended mnemonic

Nemanja Ivanovic via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jan 31 21:54:51 PST 2017


nemanjai updated this revision to Diff 86576.
nemanjai added a comment.

Provide both of the extended mnemonics for MFVSRD and add/update tests for them.

Please note that changes to test case `p8-scalar_vector_conversions.ll` may seem unrelated, but the unoptimized IR (no mem2reg) produces different mnemonics in some cases and not others (i.e. depending on which source register is selected). This update just locks the parameter registers to what the calling convention says and thereby fixes the mnemonic choice.


Repository:
  rL LLVM

https://reviews.llvm.org/D29177

Files:
  lib/Target/PowerPC/PPCInstrVSX.td
  test/CodeGen/PowerPC/bitcasts-direct-move.ll
  test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
  test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
  test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
  test/MC/Disassembler/PowerPC/vsx.txt
  test/MC/PowerPC/vsx.s

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D29177.86576.patch
Type: text/x-patch
Size: 49749 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170201/dabca135/attachment.bin>


More information about the llvm-commits mailing list