[PATCH] D27586: AMDGPU/SI: Add llvm.amdgcn.s.buffer.load intrinsic

[Tom Stellard via Phabricator via llvm-commits]

tstellarAMD added a comment.

In https://reviews.llvm.org/D27586#662432, @tstellarAMD wrote:

> In https://reviews.llvm.org/D27586#662394, @mareko wrote:
>
> > How is this different from using amdgcn.buffer.load if https://reviews.llvm.org/D28993 lands (which is not certain)?
>
>
> I don't think it's legal to select amdgcn.buffer.load to SMRD unless you can prove that it is uniform.  llvm.amdgcn.s.buffer.load is known to always be uniform.




================
Comment at: lib/Target/AMDGPU/AMDGPU.h:172
 
+  CONSTANT_ADDRESS_W_RSRC = 42,
   // Some places use this if the address space can't be determined.
----------------
arsenm wrote:
> Why 42?
4 dword  resource size for address space 2


================
Comment at: lib/Target/AMDGPU/AMDGPUTargetMachine.cpp:167
   // flat.
-  return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
+  return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p42:128:128"
          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
----------------
arsenm wrote:
> Does this need to specify non-integral? Also there are a handful of places that assume 64-bit max we should take care of
We want to be able to use inttoptr, so I don't think we can say non-integral.  Do you know where any of these places are?


https://reviews.llvm.org/D27586