[llvm] r293546 - GlobalISel: account for differing exception selector sizes.
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 30 12:52:43 PST 2017
Author: tnorthover
Date: Mon Jan 30 14:52:42 2017
New Revision: 293546
URL: http://llvm.org/viewvc/llvm-project?rev=293546&view=rev
Log:
GlobalISel: account for differing exception selector sizes.
For some reason the exception selector register must be a pointer (that's
assumed by SDag); on the other hand, it gets moved into an IR-level type which
might be entirely different (i32 on AArch64). IRTranslator needs to be aware of
this.
Modified:
llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
Modified: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=293546&r1=293545&r2=293546&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp Mon Jan 30 14:52:42 2017
@@ -801,8 +801,17 @@ bool IRTranslator::translateLandingPad(c
if (unsigned Reg = TLI.getExceptionSelectorRegister(PersonalityFn)) {
MBB.addLiveIn(Reg);
+
+ // N.b. the exception selector register always has pointer type and may not
+ // match the actual IR-level type in the landingpad so an extra cast is
+ // needed.
+ unsigned PtrVReg = MRI->createGenericVirtualRegister(Tys[0]);
+ MIRBuilder.buildCopy(PtrVReg, Reg);
+
unsigned VReg = MRI->createGenericVirtualRegister(Tys[1]);
- MIRBuilder.buildCopy(VReg, Reg);
+ MIRBuilder.buildInstr(TargetOpcode::G_PTRTOINT)
+ .addDef(VReg)
+ .addUse(PtrVReg);
Regs.push_back(VReg);
Offsets.push_back(Tys[0].getSizeInBits());
}
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll?rev=293546&r1=293545&r2=293546&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll Mon Jan 30 14:52:42 2017
@@ -19,7 +19,8 @@ declare i32 @llvm.eh.typeid.for(i8*)
; CHECK: [[BAD]] (landing-pad):
; CHECK: EH_LABEL
; CHECK: [[PTR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[SEL:%[0-9]+]](s32) = COPY %x1
+; CHECK: [[SEL_PTR:%[0-9]+]](p0) = COPY %x1
+; CHECK: [[SEL:%[0-9]+]](s32) = G_PTRTOINT [[SEL_PTR]]
; CHECK: [[PTR_SEL:%[0-9]+]](s128) = G_SEQUENCE [[PTR]](p0), 0, [[SEL]](s32), 64
; CHECK: [[PTR_RET:%[0-9]+]](s64), [[SEL_RET:%[0-9]+]](s32) = G_EXTRACT [[PTR_SEL]](s128), 0, 64
; CHECK: %x0 = COPY [[PTR_RET]]
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll?rev=293546&r1=293545&r2=293546&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll Mon Jan 30 14:52:42 2017
@@ -15,7 +15,8 @@ declare void @_Unwind_Resume(i8*)
; CHECK: [[LP]] (landing-pad):
; CHECK: EH_LABEL
; CHECK: [[PTR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[SEL:%[0-9]+]](s32) = COPY %x1
+; CHECK: [[SEL_PTR:%[0-9]+]](p0) = COPY %x1
+; CHECK: [[SEL:%[0-9]+]](s32) = G_PTRTOINT [[SEL_PTR]]
; CHECK-NOT: G_SEQUENCE
; CHECK-NOT: G_EXTRACT
; CHECK: G_STORE [[PTR]](p0), {{%[0-9]+}}(p0)
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