[PATCH] D10533: [AArch64][ARM] Match interleaved memory accesses into ldN/stN/vldN/vstN intrinsics.

[Matthias Braun via Phabricator via llvm-commits]

MatzeB added a comment.

Is there a reason this was implemented as an IR pass and not at the SelectionDAG level?


Repository:
  rL LLVM

https://reviews.llvm.org/D10533