[llvm] r293507 - [InstCombine] enable (X <<nsw C1) >>s C2 --> X <<nsw (C1-C2) for vectors with splat constants

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Mon Jan 30 11:19:32 2017
New Revision: 293507

URL: http://llvm.org/viewvc/llvm-project?rev=293507&view=rev
Log:
[InstCombine] enable (X <<nsw C1) >>s C2 --> X <<nsw (C1-C2) for vectors with splat constants

Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp
    llvm/trunk/test/Transforms/InstCombine/shift.ll

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp?rev=293507&r1=293506&r2=293507&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp Mon Jan 30 11:19:32 2017
@@ -370,24 +370,7 @@ foldShiftByConstOfShiftByConst(BinaryOpe
     return nullptr;
 
   IntegerType *Ty = cast<IntegerType>(I.getType());
-  if (ShiftAmt1 < ShiftAmt2) {
-    uint32_t ShiftDiff = ShiftAmt2 - ShiftAmt1;
-
-    // We can't handle (X << C1) >>s C2, it shifts arbitrary bits in. However,
-    // we can handle (X <<nsw C1) >>s C2 since it only shifts in sign bits.
-    if (I.getOpcode() == Instruction::AShr &&
-        ShiftOp->getOpcode() == Instruction::Shl) {
-      if (ShiftOp->hasNoSignedWrap()) {
-        // (X <<nsw C1) >>s C2 --> X >>s (C2-C1)
-        ConstantInt *ShiftDiffCst = ConstantInt::get(Ty, ShiftDiff);
-        BinaryOperator *NewAShr =
-            BinaryOperator::Create(Instruction::AShr, X, ShiftDiffCst);
-        NewAShr->setIsExact(I.isExact());
-        return NewAShr;
-      }
-    }
-  } else {
-    assert(ShiftAmt2 < ShiftAmt1);
+  if (ShiftAmt2 < ShiftAmt1) {
     uint32_t ShiftDiff = ShiftAmt1 - ShiftAmt2;
 
     // (X >>?exact C1) << C2 --> X >>?exact (C1-C2)
@@ -800,7 +783,8 @@ Instruction *InstCombiner::visitAShr(Bin
   if (Instruction *R = commonShiftTransforms(I))
     return R;
 
-  unsigned BitWidth = I.getType()->getScalarSizeInBits();
+  Type *Ty = I.getType();
+  unsigned BitWidth = Ty->getScalarSizeInBits();
   const APInt *ShAmtAPInt;
   if (match(Op1, m_APInt(ShAmtAPInt))) {
     unsigned ShAmt = ShAmtAPInt->getZExtValue();
@@ -811,7 +795,19 @@ Instruction *InstCombiner::visitAShr(Bin
     Value *X;
     if (match(Op0, m_Shl(m_ZExt(m_Value(X)), m_Specific(Op1))) &&
         ShAmt == BitWidth - X->getType()->getScalarSizeInBits())
-      return new SExtInst(X, I.getType());
+      return new SExtInst(X, Ty);
+
+    // We can't handle (X << C1) >>s C2. It shifts arbitrary bits in. However,
+    // we can handle (X <<nsw C1) >>s C2 since it only shifts in sign bits.
+    const APInt *ShlAmtAPInt;
+    if (match(Op0, m_NSWShl(m_Value(X), m_APInt(ShlAmtAPInt))) &&
+        ShlAmtAPInt->ult(*ShAmtAPInt)) {
+      // (X <<nsw C1) >>s C2 --> X >>s (C2 - C1)
+      Constant *ShiftDiff = ConstantInt::get(Ty, *ShAmtAPInt - *ShlAmtAPInt);
+      BinaryOperator *NewAShr = BinaryOperator::CreateAShr(X, ShiftDiff);
+      NewAShr->setIsExact(I.isExact());
+      return NewAShr;
+    }
 
     // If the shifted-out value is known-zero, then this is an exact shift.
     if (!I.isExact() &&

Modified: llvm/trunk/test/Transforms/InstCombine/shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/shift.ll?rev=293507&r1=293506&r2=293507&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/shift.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/shift.ll Mon Jan 30 11:19:32 2017
@@ -895,15 +895,15 @@ define i32 @test50(i32 %x) {
 }
 
 ; (X <<nsw C1) >>s C2 --> X >>s (C2-C1)
+; Also, check that exact is propagated.
 
 define <2 x i32> @test50_splat_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test50_splat_vec(
-; CHECK-NEXT:    [[A:%.*]] = shl nsw <2 x i32> %x, <i32 1, i32 1>
-; CHECK-NEXT:    [[B:%.*]] = ashr <2 x i32> [[A]], <i32 3, i32 3>
+; CHECK-NEXT:    [[B:%.*]] = ashr exact <2 x i32> %x, <i32 2, i32 2>
 ; CHECK-NEXT:    ret <2 x i32> [[B]]
 ;
   %A = shl nsw <2 x i32> %x, <i32 1, i32 1>
-  %B = ashr <2 x i32> %A, <i32 3, i32 3>
+  %B = ashr exact <2 x i32> %A, <i32 3, i32 3>
   ret <2 x i32> %B
 }