[llvm] r293483 - TableGen: Fix infinite recursion in RegisterBankEmitter

[Tom Stellard via llvm-commits]

Author: tstellar
Date: Mon Jan 30 09:07:01 2017
New Revision: 293483

URL: http://llvm.org/viewvc/llvm-project?rev=293483&view=rev
Log:
TableGen: Fix infinite recursion in RegisterBankEmitter

Summary:
AMDGPU has two register classes with the same set of registers, and this
was causing this tablegen backend would get stuck in infinite recursion.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: tpr, wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D29049

Added:
    llvm/trunk/test/TableGen/RegisterBankEmitter.td
Modified:
    llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp

Added: llvm/trunk/test/TableGen/RegisterBankEmitter.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/RegisterBankEmitter.td?rev=293483&view=auto
==============================================================================
--- llvm/trunk/test/TableGen/RegisterBankEmitter.td (added)
+++ llvm/trunk/test/TableGen/RegisterBankEmitter.td Mon Jan 30 09:07:01 2017
@@ -0,0 +1,15 @@
+// RUN: llvm-tblgen -gen-register-bank -I %p/../../include %s | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+def MyTarget : Target;
+def R0 : Register<"r0">;
+let Size = 32 in {
+  def ClassA : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
+  def ClassB : RegisterClass<"MyTarget", [i1], 32, (add ClassA)>;
+}
+
+// CHECK: GPRRegBankCoverageData
+// CHECK: MyTarget::ClassARegClassID
+// CHECK: MyTarget::ClassBRegClassID
+def GPRRegBank : RegisterBank<"GPR", [ClassA]>;

Modified: llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp?rev=293483&r1=293482&r2=293483&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp Mon Jan 30 09:07:01 2017
@@ -168,7 +168,14 @@ void RegisterBankEmitter::emitBaseClassD
 static void visitRegisterBankClasses(
     CodeGenRegBank &RegisterClassHierarchy, const CodeGenRegisterClass *RC,
     const Twine Kind,
-    std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn) {
+    std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn,
+    SmallPtrSetImpl<const CodeGenRegisterClass *> &VisitedRCs) {
+
+  // Make sure we only visit each class once to avoid infinite loops.
+  if (VisitedRCs.count(RC))
+    return;
+  VisitedRCs.insert(RC);
+
   // Visit each explicitly named class.
   VisitFn(RC, Kind.str());
 
@@ -180,7 +187,7 @@ static void visitRegisterBankClasses(
     if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass))
       visitRegisterBankClasses(RegisterClassHierarchy, &PossibleSubclass,
                                TmpKind + " " + RC->getName() + " subclass",
-                               VisitFn);
+                               VisitFn, VisitedRCs);
 
     // Visit each class that contains only subregisters of RC with a common
     // subregister-index.
@@ -273,6 +280,7 @@ void RegisterBankEmitter::run(raw_ostrea
 
   std::vector<RegisterBank> Banks;
   for (const auto &V : Records.getAllDerivedDefinitions("RegisterBank")) {
+    SmallPtrSet<const CodeGenRegisterClass *, 8> VisitedRCs;
     RegisterBank Bank(*V);
 
     for (const CodeGenRegisterClass *RC :
@@ -282,7 +290,7 @@ void RegisterBankEmitter::run(raw_ostrea
           [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) {
             DEBUG(dbgs() << "Added " << RC->getName() << "(" << Kind << ")\n");
             Bank.addRegisterClass(RC);
-          });
+          }, VisitedRCs);
     }
 
     Banks.push_back(Bank);