[llvm] r293403 - [X86] Fix vector ANDN matching to work correctly when both inputs to the AND are XORs.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Sat Jan 28 17:52:09 2017
New Revision: 293403

URL: http://llvm.org/viewvc/llvm-project?rev=293403&view=rev
Log:
[X86] Fix vector ANDN matching to work correctly when both inputs to the AND are XORs.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/vec_logical.ll
    llvm/trunk/test/CodeGen/X86/vsplit-and.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=293403&r1=293402&r2=293403&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Jan 28 17:52:09 2017
@@ -30656,20 +30656,15 @@ static SDValue combineANDXORWithAllOnesI
   if (VT != MVT::v2i64 && VT != MVT::v4i64 && VT != MVT::v8i64)
     return SDValue();
 
-  // Canonicalize XOR to the left.
-  if (N1.getOpcode() == ISD::XOR)
-    std::swap(N0, N1);
+  if (N0.getOpcode() == ISD::XOR &&
+      ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
+    return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
+
+  if (N1.getOpcode() == ISD::XOR &&
+      ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
+    return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
 
-  if (N0.getOpcode() != ISD::XOR)
-    return SDValue();
-
-  SDValue N00 = N0->getOperand(0);
-  SDValue N01 = N0->getOperand(1);
-
-  if (!ISD::isBuildVectorAllOnes(N01.getNode()))
-    return SDValue();
-
-  return DAG.getNode(X86ISD::ANDNP, DL, VT, N00, N1);
+  return SDValue();
 }
 
 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized

Modified: llvm/trunk/test/CodeGen/X86/vec_logical.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_logical.ll?rev=293403&r1=293402&r2=293403&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_logical.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_logical.ll Sat Jan 28 17:52:09 2017
@@ -89,18 +89,14 @@ entry:
 define <2 x i64> @andn_double_xor(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
 ; SSE-LABEL: andn_double_xor:
 ; SSE:       # BB#0:
-; SSE-NEXT:    pcmpeqd %xmm3, %xmm3
-; SSE-NEXT:    pxor %xmm3, %xmm0
-; SSE-NEXT:    pxor %xmm2, %xmm1
-; SSE-NEXT:    pand %xmm1, %xmm0
+; SSE-NEXT:    xorps %xmm2, %xmm1
+; SSE-NEXT:    andnps %xmm1, %xmm0
 ; SSE-NEXT:    retl
 ;
 ; AVX-LABEL: andn_double_xor:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpcmpeqd %xmm3, %xmm3, %xmm3
-; AVX-NEXT:    vpxor %xmm3, %xmm0, %xmm0
-; AVX-NEXT:    vpxor %xmm2, %xmm1, %xmm1
-; AVX-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vxorps %xmm2, %xmm1, %xmm1
+; AVX-NEXT:    vandnps %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retl
   %1 = xor <2 x i64> %a, <i64 -1, i64 -1>
   %2 = xor <2 x i64> %b, %c

Modified: llvm/trunk/test/CodeGen/X86/vsplit-and.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vsplit-and.ll?rev=293403&r1=293402&r2=293403&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vsplit-and.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vsplit-and.ll Sat Jan 28 17:52:09 2017
@@ -6,11 +6,11 @@ define void @t0(<2 x i64>* %dst, <2 x i6
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    pxor %xmm2, %xmm2
 ; CHECK-NEXT:    pcmpeqq %xmm2, %xmm0
-; CHECK-NEXT:    pcmpeqd %xmm3, %xmm3
-; CHECK-NEXT:    pxor %xmm0, %xmm3
 ; CHECK-NEXT:    pcmpeqq %xmm2, %xmm1
-; CHECK-NEXT:    pandn %xmm3, %xmm1
-; CHECK-NEXT:    movdqa %xmm1, (%rdi)
+; CHECK-NEXT:    pcmpeqd %xmm2, %xmm2
+; CHECK-NEXT:    pxor %xmm1, %xmm2
+; CHECK-NEXT:    pandn %xmm2, %xmm0
+; CHECK-NEXT:    movdqa %xmm0, (%rdi)
 ; CHECK-NEXT:    retq
   %cmp1 = icmp ne <2 x i64> %src1, zeroinitializer
   %cmp2 = icmp ne <2 x i64> %src2, zeroinitializer