[llvm] r292713 - [X86] Don't allow commuting to form phsub operations.

[Hans Wennborg via llvm-commits]

Merged, together with r292712, to the 4.0 branch in r293299.

On Fri, Jan 20, 2017 at 10:59 PM, Craig Topper via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: ctopper
> Date: Sat Jan 21 00:59:38 2017
> New Revision: 292713
>
> URL: http://llvm.org/viewvc/llvm-project?rev=292713&view=rev
> Log:
> [X86] Don't allow commuting to form phsub operations.
>
> Fixes PR31714.
>
> Modified:
>     llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>     llvm/trunk/test/CodeGen/X86/phaddsub.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=292713&r1=292712&r2=292713&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Jan 21 00:59:38 2017
> @@ -33864,11 +33864,11 @@ static SDValue combineSub(SDNode *N, Sel
>      }
>    }
>
> -  // Try to synthesize horizontal adds from adds of shuffles.
> +  // Try to synthesize horizontal subs from subs of shuffles.
>    EVT VT = N->getValueType(0);
>    if (((Subtarget.hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
>         (Subtarget.hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
> -      isHorizontalBinOp(Op0, Op1, true))
> +      isHorizontalBinOp(Op0, Op1, false))
>      return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
>
>    return OptimizeConditionalInDecrement(N, DAG);
>
> Modified: llvm/trunk/test/CodeGen/X86/phaddsub.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/phaddsub.ll?rev=292713&r1=292712&r2=292713&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/phaddsub.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/phaddsub.ll Sat Jan 21 00:59:38 2017
> @@ -229,12 +229,31 @@ define <4 x i32> @phsubd4(<4 x i32> %x)
>  define <8 x i16> @phsubw1_reverse(<8 x i16> %x, <8 x i16> %y) {
>  ; SSSE3-LABEL: phsubw1_reverse:
>  ; SSSE3:       # BB#0:
> -; SSSE3-NEXT:    phsubw %xmm1, %xmm0
> +; SSSE3-NEXT:    movdqa {{.*#+}} xmm3 = [2,3,6,7,10,11,14,15,14,15,10,11,12,13,14,15]
> +; SSSE3-NEXT:    movdqa %xmm1, %xmm4
> +; SSSE3-NEXT:    pshufb %xmm3, %xmm4
> +; SSSE3-NEXT:    movdqa %xmm0, %xmm2
> +; SSSE3-NEXT:    pshufb %xmm3, %xmm2
> +; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
> +; SSSE3-NEXT:    movdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
> +; SSSE3-NEXT:    pshufb %xmm3, %xmm1
> +; SSSE3-NEXT:    pshufb %xmm3, %xmm0
> +; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
> +; SSSE3-NEXT:    psubw %xmm0, %xmm2
> +; SSSE3-NEXT:    movdqa %xmm2, %xmm0
>  ; SSSE3-NEXT:    retq
>  ;
>  ; AVX-LABEL: phsubw1_reverse:
>  ; AVX:       # BB#0:
> -; AVX-NEXT:    vphsubw %xmm1, %xmm0, %xmm0
> +; AVX-NEXT:    vmovdqa {{.*#+}} xmm2 = [2,3,6,7,10,11,14,15,14,15,10,11,12,13,14,15]
> +; AVX-NEXT:    vpshufb %xmm2, %xmm1, %xmm3
> +; AVX-NEXT:    vpshufb %xmm2, %xmm0, %xmm2
> +; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
> +; AVX-NEXT:    vmovdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
> +; AVX-NEXT:    vpshufb %xmm3, %xmm1, %xmm1
> +; AVX-NEXT:    vpshufb %xmm3, %xmm0, %xmm0
> +; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
> +; AVX-NEXT:    vpsubw %xmm0, %xmm2, %xmm0
>  ; AVX-NEXT:    retq
>    %a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
>    %b = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
> @@ -245,12 +264,18 @@ define <8 x i16> @phsubw1_reverse(<8 x i
>  define <4 x i32> @phsubd1_reverse(<4 x i32> %x, <4 x i32> %y) {
>  ; SSSE3-LABEL: phsubd1_reverse:
>  ; SSSE3:       # BB#0:
> -; SSSE3-NEXT:    phsubd %xmm1, %xmm0
> +; SSSE3-NEXT:    movaps %xmm0, %xmm2
> +; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,3],xmm1[1,3]
> +; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
> +; SSSE3-NEXT:    psubd %xmm0, %xmm2
> +; SSSE3-NEXT:    movdqa %xmm2, %xmm0
>  ; SSSE3-NEXT:    retq
>  ;
>  ; AVX-LABEL: phsubd1_reverse:
>  ; AVX:       # BB#0:
> -; AVX-NEXT:    vphsubd %xmm1, %xmm0, %xmm0
> +; AVX-NEXT:    vshufps {{.*#+}} xmm2 = xmm0[1,3],xmm1[1,3]
> +; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
> +; AVX-NEXT:    vpsubd %xmm0, %xmm2, %xmm0
>  ; AVX-NEXT:    retq
>    %a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
>    %b = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
>
>
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