[PATCH] D29219: [AArch64][TableGen] Skip tied result operands for InstAlias

[Graham Hunter via Phabricator via llvm-commits]

huntergr created this revision.
Herald added subscribers: rengolin, aemerson.
Herald added a reviewer: javed.absar.

This patch checks the number of operands in the resulting
instruction instead of just the alias, then skips over
tied operands when generating the printing method.

This allows us to generate the preferred assembly syntax
for the AArch64 'ins' instruction, which should always be
displayed as 'mov' according to the ARMARM.

Several unit tests have changed as a result, but only to
reflect the preferred disassembly.

Some other InstAlias patterns (movk/bic/orr) needed a
slight adjustment to stop them becoming the default
and breaking other unit tests.


https://reviews.llvm.org/D29219

Files:
  lib/Target/AArch64/AArch64InstrInfo.td
  test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
  test/CodeGen/AArch64/arm64-build-vector.ll
  test/CodeGen/AArch64/arm64-dup.ll
  test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
  test/CodeGen/AArch64/arm64-neon-copy.ll
  test/CodeGen/AArch64/arm64-smaxv.ll
  test/CodeGen/AArch64/arm64-sminv.ll
  test/CodeGen/AArch64/arm64-stp.ll
  test/CodeGen/AArch64/arm64-umaxv.ll
  test/CodeGen/AArch64/arm64-uminv.ll
  test/CodeGen/AArch64/arm64-vaddv.ll
  test/CodeGen/AArch64/arm64-vcombine.ll
  test/CodeGen/AArch64/arm64-vector-insertion.ll
  test/CodeGen/AArch64/bitreverse.ll
  test/CodeGen/AArch64/concat_vector-scalar-combine.ll
  test/CodeGen/AArch64/fp16-v16-instructions.ll
  test/CodeGen/AArch64/fp16-v4-instructions.ll
  test/CodeGen/AArch64/fp16-v8-instructions.ll
  test/CodeGen/AArch64/fp16-vector-shuffle.ll
  test/CodeGen/AArch64/vector-fcopysign.ll
  test/MC/AArch64/arm64-advsimd.s
  test/MC/Disassembler/AArch64/arm64-advsimd.txt
  utils/TableGen/AsmWriterEmitter.cpp

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