[PATCH] D29127: [ARM] Classification Improvements to ARM Sched-Model. NFCI.

[Diana Picus via Phabricator via llvm-commits]

rovka added inline comments.


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Comment at: lib/Target/ARM/ARMInstrInfo.td:4079
+           Requires<[IsARM, HasV5TE]>,
+           Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
 
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I see you're modelling IIC_iMUL16 the same as IIC_iMUL32, but they don't seem to be exactly identical in any of the models (A9, A8, V6).  Same for IIC_iMAC16.


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Comment at: test/CodeGen/ARM/misched-int-basic.ll:41
+  %conv = sext i32 %add2 to i64
+  %mul3 = mul nsw i64 %conv, %conv
+  ret i64 %mul3
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Can you also add a test for 64-bit mac?


https://reviews.llvm.org/D29127