[PATCH] D28696: DAG: Constant fold fp16_to_fp/fp16_to_fp

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon accepted this revision.
RKSimon added a comment.
This revision is now accepted and ready to land.

LGTM - How come we haven't been able to remove these intrinsics and just use (f32 fpext(f16 bitcast(i16 src))) style patterns?



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Comment at: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:3335
       case ISD::FP_TO_SINT:
       case ISD::FP_TO_UINT:
       case ISD::TRUNCATE:
----------------
arsenm wrote:
> arsenm wrote:
> > arsenm wrote:
> > > RKSimon wrote:
> > > > Add ISD::FP_TO_FP16: to vector constant folding?
> > > I'm not sure these support vectors?
> > The intrinsics do not, but I guess it could differ for the node
> The intrinsics are turned into the normal FP casts instructions, so this only matters for targets using these for legalization purposes. It looks like only AMDGPU is doing this now, so I have no vector use/way to test it
Sorry I was getting this mixed up with basic fpext/fptrunc half handling. 


https://reviews.llvm.org/D28696