[PATCH] D29105: Fix regalloc assignment of overlapping registers

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec marked 2 inline comments as done.
rampitec added inline comments.


================
Comment at: lib/CodeGen/SplitKit.cpp:535
+          if (TRI.getSubRegIndexLaneMask(I) == LM) {
+            SubIdx = I;
+            break;
----------------
alex-t wrote:
> alex-t wrote:
> > What if in parent LiveInterval there are more then one subrange (i.e. several not adjacent lanes are in use) ?  Let's say we copy sub0 and sub2.
> > LaneMask will be 1010 and the condition "TRI.getSubRegIndexLaneMask(I) == LM" will never met.
> > Given the assert below this, why this never expected to happen?
> Oops... forget it )  I missed that getSubRegIndexLaneMask and setSubreg treat the parameter as a plane integer...
It looks like it does not happen, but in case if lane combination is not supported by target here is the assert. To me it is better to see an assert rather than silently clobber register.


Repository:
  rL LLVM

https://reviews.llvm.org/D29105