[PATCH] D29105: Fix regalloc assignment of overlapping registers

[Alexander via Phabricator via llvm-commits]

alex-t added inline comments.


================
Comment at: lib/CodeGen/SplitKit.cpp:535
+          if (TRI.getSubRegIndexLaneMask(I) == LM) {
+            SubIdx = I;
+            break;
----------------
What if in parent LiveInterval there are more then one subrange (i.e. several not adjacent lanes are in use) ?  Let's say we copy sub0 and sub2.
LaneMask will be 1010 and the condition "TRI.getSubRegIndexLaneMask(I) == LM" will never met.
Given the assert below this, why this never expected to happen?


Repository:
  rL LLVM

https://reviews.llvm.org/D29105