[llvm] r292924 - [X86][SSE] Add explicit braces to avoid -Wdangling-else warning.

[Martin Bohme via llvm-commits]

Author: mboehme
Date: Tue Jan 24 06:31:30 2017
New Revision: 292924

URL: http://llvm.org/viewvc/llvm-project?rev=292924&view=rev
Log:
[X86][SSE] Add explicit braces to avoid -Wdangling-else warning.

Reviewers: RKSimon

Subscribers: llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D29076

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=292924&r1=292923&r2=292924&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jan 24 06:31:30 2017
@@ -30478,11 +30478,12 @@ static SDValue combineVectorShift(SDNode
   // Out of range logical bit shifts are guaranteed to be zero.
   // Out of range arithmetic bit shifts splat the sign bit.
   APInt ShiftVal = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
-  if (ShiftVal.zextOrTrunc(8).uge(NumBitsPerElt))
+  if (ShiftVal.zextOrTrunc(8).uge(NumBitsPerElt)) {
     if (LogicalShift)
       return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, SDLoc(N));
     else
       ShiftVal = NumBitsPerElt - 1;
+  }
 
   SDValue N0 = N->getOperand(0);