[llvm] r292893 - AMDGPU : Add trap handler support.
Wei Ding via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 23 22:41:21 PST 2017
Author: wdng
Date: Tue Jan 24 00:41:21 2017
New Revision: 292893
URL: http://llvm.org/viewvc/llvm-project?rev=292893&view=rev
Log:
AMDGPU : Add trap handler support.
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
llvm/trunk/test/CodeGen/AMDGPU/trap.ll
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp?rev=292893&r1=292892&r2=292893&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp Tue Jan 24 00:41:21 2017
@@ -190,7 +190,8 @@ bool AMDGPUAnnotateKernelFeatures::runOn
static const StringRef HSAIntrinsicToAttr[][2] = {
{ "llvm.amdgcn.dispatch.ptr", "amdgpu-dispatch-ptr" },
{ "llvm.amdgcn.queue.ptr", "amdgpu-queue-ptr" },
- { "llvm.amdgcn.dispatch.id", "amdgpu-dispatch-id" }
+ { "llvm.amdgcn.dispatch.id", "amdgpu-dispatch-id" },
+ { "llvm.trap", "amdgpu-queue-ptr" }
};
// TODO: We should not add the attributes if the known compile time workgroup
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=292893&r1=292892&r2=292893&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Tue Jan 24 00:41:21 2017
@@ -272,7 +272,7 @@ SITargetLowering::SITargetLowering(const
// On SI this is s_memtime and s_memrealtime on VI.
setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
- setOperationAction(ISD::TRAP, MVT::Other, Custom);
+ setOperationAction(ISD::TRAP, MVT::Other, Legal);
setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
@@ -1780,6 +1780,29 @@ MachineBasicBlock *SITargetLowering::Emi
}
switch (MI.getOpcode()) {
+ case AMDGPU::S_TRAP_PSEUDO: {
+ DebugLoc DL = MI.getDebugLoc();
+ BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), AMDGPU::VGPR0)
+ .addImm(1);
+
+ MachineFunction *MF = BB->getParent();
+ SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
+ unsigned UserSGPR = Info->getQueuePtrUserSGPR();
+ assert(UserSGPR != AMDGPU::NoRegister);
+
+ if (!BB->isLiveIn(UserSGPR))
+ BB->addLiveIn(UserSGPR);
+
+ BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), AMDGPU::SGPR0_SGPR1)
+ .addReg(UserSGPR);
+ BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_TRAP)).addImm(0x1)
+ .addReg(AMDGPU::VGPR0, RegState::Implicit)
+ .addReg(AMDGPU::SGPR0_SGPR1, RegState::Implicit);
+
+ MI.eraseFromParent();
+ return BB;
+ }
+
case AMDGPU::SI_INIT_M0:
BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(),
TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
@@ -1949,7 +1972,6 @@ SDValue SITargetLowering::LowerOperation
return lowerINSERT_VECTOR_ELT(Op, DAG);
case ISD::EXTRACT_VECTOR_ELT:
return lowerEXTRACT_VECTOR_ELT(Op, DAG);
- case ISD::TRAP: return lowerTRAP(Op, DAG);
case ISD::FP_ROUND:
return lowerFP_ROUND(Op, DAG);
}
@@ -2423,23 +2445,6 @@ SDValue SITargetLowering::LowerGlobalAdd
MachineMemOperand::MOInvariant);
}
-SDValue SITargetLowering::lowerTRAP(SDValue Op,
- SelectionDAG &DAG) const {
- const MachineFunction &MF = DAG.getMachineFunction();
- DiagnosticInfoUnsupported NoTrap(*MF.getFunction(),
- "trap handler not supported",
- Op.getDebugLoc(),
- DS_Warning);
- DAG.getContext()->diagnose(NoTrap);
-
- // Emit s_endpgm.
-
- // FIXME: This should really be selected to s_trap, but that requires
- // setting up the trap handler for it o do anything.
- return DAG.getNode(AMDGPUISD::ENDPGM, SDLoc(Op), MVT::Other,
- Op.getOperand(0));
-}
-
SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain,
const SDLoc &DL, SDValue V) const {
// We can't use S_MOV_B32 directly, because there is no way to specify m0 as
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=292893&r1=292892&r2=292893&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Tue Jan 24 00:41:21 2017
@@ -111,6 +111,13 @@ def V_MOV_B64_PSEUDO : VPseudoInstSI <(o
(ins VSrc_b64:$src0)>;
} // End let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC]
+def S_TRAP_PSEUDO : VPseudoInstSI <(outs), (ins),
+ [(trap)]> {
+ let hasSideEffects = 1;
+ let SALU = 1;
+ let usesCustomInserter = 1;
+}
+
let usesCustomInserter = 1, SALU = 1 in {
def GET_GROUPSTATICSIZE : PseudoInstSI <(outs SReg_32:$sdst), (ins),
[(set SReg_32:$sdst, (int_amdgcn_groupstaticsize))]>;
Modified: llvm/trunk/test/CodeGen/AMDGPU/trap.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/trap.ll?rev=292893&r1=292892&r2=292893&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/trap.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/trap.ll Tue Jan 24 00:41:21 2017
@@ -1,12 +1,11 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN %s
-
-; GCN: warning: <unknown>:0:0: in function trap void (): trap handler not supported
+; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN %s
declare void @llvm.trap() #0
; GCN-LABEL: {{^}}trap:
-; GCN: s_endpgm
-; GCN-NEXT: s_endpgm
+; GCN: v_mov_b32_e32 v0, 1
+; GCN: s_mov_b64 s[0:1], s[4:5]
+; GCN: s_trap 1
define void @trap() {
call void @llvm.trap()
ret void
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