[llvm] r292836 - [Hexagon] Explicitly reserve aliases of reserved registers

[Matthias Braun via llvm-commits]

Thanks for the quick reaction to D28881. BTW: You may try adding `assert(checkAllSuperRegsMarked(Reserved));` to avoid this creeping up again in the future. (I didn't add that call to all targets back then because depending on the target you need to specify exception which are hard to figure out if you do not know a target)

- Matthias

> On Jan 23, 2017, at 2:13 PM, Krzysztof Parzyszek via llvm-commits <llvm-commits at lists.llvm.org> wrote:
> 
> Author: kparzysz
> Date: Mon Jan 23 16:13:05 2017
> New Revision: 292836
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=292836&view=rev
> Log:
> [Hexagon] Explicitly reserve aliases of reserved registers
> 
> Modified:
>    llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
>    llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td
> 
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp?rev=292836&r1=292835&r2=292836&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp Mon Jan 23 16:13:05 2017
> @@ -139,19 +139,26 @@ BitVector HexagonRegisterInfo::getReserv
>   Reserved.set(Hexagon::R29);
>   Reserved.set(Hexagon::R30);
>   Reserved.set(Hexagon::R31);
> -  Reserved.set(Hexagon::PC);
> -  Reserved.set(Hexagon::D14);
> -  Reserved.set(Hexagon::D15);
> -  Reserved.set(Hexagon::LC0);
> -  Reserved.set(Hexagon::LC1);
> -  Reserved.set(Hexagon::SA0);
> -  Reserved.set(Hexagon::SA1);
> -  Reserved.set(Hexagon::UGP);
> -  Reserved.set(Hexagon::GP);
> -  Reserved.set(Hexagon::CS0);
> -  Reserved.set(Hexagon::CS1);
> -  Reserved.set(Hexagon::CS);
> -  Reserved.set(Hexagon::USR);
> +  Reserved.set(Hexagon::SA0); // C0
> +  Reserved.set(Hexagon::LC0); // C1
> +  Reserved.set(Hexagon::SA1); // C2
> +  Reserved.set(Hexagon::LC1); // C3
> +  Reserved.set(Hexagon::USR); // C8
> +  Reserved.set(Hexagon::PC);  // C9
> +  Reserved.set(Hexagon::UGP); // C10
> +  Reserved.set(Hexagon::GP);  // C11
> +  Reserved.set(Hexagon::CS0); // C12
> +  Reserved.set(Hexagon::CS1); // C13
> +
> +  // Out of the control registers, only C8 is explicitly defined in
> +  // HexagonRegisterInfo.td. If others are defined, make sure to add
> +  // them here as well.
> +  Reserved.set(Hexagon::C8);
> +  Reserved.set(Hexagon::USR_OVF);
> +
> +  for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x))
> +    markSuperRegs(Reserved, x);
> +
>   return Reserved;
> }
> 
> 
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td?rev=292836&r1=292835&r2=292836&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td Mon Jan 23 16:13:05 2017
> @@ -146,6 +146,8 @@ let Namespace = "Hexagon" in {
>   def LC1  : Rc<3,  "lc1",       ["c3"]>,   DwarfRegNum<[70]>;
>   def P3_0 : Rc<4,  "p3:0",      ["c4"], [P0, P1, P2, P3]>,
>                                             DwarfRegNum<[71]>;
> +  // When defining more Cn registers, make sure to explicitly mark them
> +  // as reserved in HexagonRegisterInfo.cpp.
>   def C5   : Rc<5,  "c5",        ["c5"]>,   DwarfRegNum<[72]>; // future use
>   def C6   : Rc<6,  "c6",        [], [M0]>, DwarfRegNum<[73]>;
>   def C7   : Rc<7,  "c7",        [], [M1]>, DwarfRegNum<[74]>;
> 
> 
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